The purpose is to monitor an incoming digital signal. If there hasn't been a high signal in 15 min then it should set an output pin to high.
We want a 15 min timer to be reset if a digital input Pin is high. If the timer reaches 0 then set a different digital Pin to high. This digital pin should be the input to some other logic (the reset on an SR latch)
Ideally we would take advantage of the sleep mode of the PSoC 3/5 as well.
You can use the Timer Component to develop the 15 minute timer. By choosing an appropraite clock input to the Timer and appropraite Period value, you can set the tmier to generate a terminal count interrupt. Once the Timer reaches its terminal count, an interrupt will be generate to indicate the completion on time period.
Same can be achived using Sleep Time as well. The Sleep Timer component is capable of generating an interrupt every 4096ms, 2048ms, 1024ms and so on. The device can be put to sleep or it can stay active and run the Sleep Timer, and it can be configured to generate and interupt every 4096 ms. During every interrupt a counter variable can be incremented. Once the counter reaches a count of 220(equivalent to 15 mins) the digital pin can be set high. However a point to be noted with Sleep Timer is the tolerance of the clock being used. The Sleep Timer uses the ILO, the tolerance value for the same can be obtained from the datasheet.
The input pin being monitored can be connected to an Interrupt Component . When the Pin goes high, interrupt will be generated and in the interrupt , the digital pin connected to the logic(SR latch) can be set to high and Timer can be reset.