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PSoC™ 5, 3 & 1

Mrinal
New Contributor II

Hi!

Is there a way to change the PWM compare value in PSOC-5LP using a hardware event? I mean a feature similar to PSOC-4, where compare buffer values can be swapped during a trigger event.

My concern is, what happens if the compare register is updated to a value less than the counter value? Since the PWM compare update algorithm can be running continuously in a non synchronized manner it is always possible to update the compare register to a value lower than the current counter value. How to avoid this?

Also, suppose  if the compare register is updated to a value less than the counter value, what happens then?

Please help

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1 Solution
Yeshwanth_KT
Employee

Hello,

There is no built-in hardware feature in PWM IP that will allow you to change Compare value, but you can follow the below workaround to solve your problem.

Method: Use the hardware event to trigger a DMA to transfer the desired compare value from memory to the compare register of the PWM. Since the DMA runs independently from the CPU, it won't consume any CPU time.

You can refer to this PSoC 6 CE to understand the usage of the DMA: http://www.cypress.com/documentation/code-examples/ce218553-psoc-r-6-mcu-pwm-triggering-dma-channel

If you write the compare value less than the counter value, the PWM will process the compare value in the next overflow cycle ( Counter will overflow and restart from beginning and the new compare value will be processed).

If the compare value is greater than the counter value, the PWM will process it in the same cycle.

Note: To avoid glitches (if you find any) use the hardware signal to reset the PWM.

Thanks,

Yeshwanth

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4 Replies
Yeshwanth_KT
Employee

Hello,

There is no built-in hardware feature in PWM IP that will allow you to change Compare value, but you can follow the below workaround to solve your problem.

Method: Use the hardware event to trigger a DMA to transfer the desired compare value from memory to the compare register of the PWM. Since the DMA runs independently from the CPU, it won't consume any CPU time.

You can refer to this PSoC 6 CE to understand the usage of the DMA: http://www.cypress.com/documentation/code-examples/ce218553-psoc-r-6-mcu-pwm-triggering-dma-channel

If you write the compare value less than the counter value, the PWM will process the compare value in the next overflow cycle ( Counter will overflow and restart from beginning and the new compare value will be processed).

If the compare value is greater than the counter value, the PWM will process it in the same cycle.

Note: To avoid glitches (if you find any) use the hardware signal to reset the PWM.

Thanks,

Yeshwanth

View solution in original post

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Mrinal
New Contributor II

Thanks Yeshwanth!

So it is clear that the PWM compare value cannot be updated instantly at the rising edge of an external signal. This is not a very good news.

I understand that the DMA can save CPU time nevertheless the DMA also probably has it's own delay. The update process will not be within one clock pulse at the rising edge.

Updating the compare value in an unsynchronized interrupt results in misfiring  of PWM. At several instances the PWM gives full duty cycle and at other instances there's a glitch. Attached is screenshot of motor driver leg.(Blue colour is Half bridge output wrt ground)

TEK0010.BMP  TEK0017.BMP

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Yeshwanth_KT
Employee

Can you specify the values of period/compare of the PWM before and after changing the values which gave you those graphs. To avoid glitches you can always latch an interrupt to the hardware signal and process the interrupt in software properly. Did you use the reset pin of the PWM as I specified in the note section of my previous answer?

Thanks,

Yeshwanth

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Mrinal
New Contributor II

Hi!

The PWM module used is a 16 bit UDB implementation with the following initialization:

Input clock = 60MHz

Period = 2999

Compare type = "less"

Dead band = 20 cycles

Ph1 and Ph2 signals are being used to drive an H-bridge leg.

The motor current control algorithm is a very basic one that increments or decrements the compare value by ONE count depending on the error. This simple function is implemented as an ISR that is triggered @ 10KHz.

if(Error_I_M1 > 0 && (PWM_1_Compare < PWM_1_Compare_Max))

        {

           PWM_1_Compare ++;

           PWM_1_WriteCompare(PWM_1_Compare);

        }

      

        if(Error_I_M1 < 0 && (PWM_1_Compare > PWM_1_Compare_Min))

        {

            PWM_1_Compare--;

            PWM_1_WriteCompare(PWM_1_Compare);

        }

The point to be noted is that between any two subsequent PWM signals there can be one one count duty cycle change. But we got outputs that jumped suddenly from say 60% to 100%.

I have now connected the ISR to the PWM output terminal of the PWM module and also reduced the clock frequency to 30MHz. There's no problem now.

But I was wondering what could have made the PWM behave in a glitchy manner earlier when the ISR was triggered from 10KHz source and not from PWM terminal.

Thanks Mrinal

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