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PSoC 5, 3 & 1

dahec_263886
New Contributor

I am designing a system with 4 PSoC 5LP boards acting as Slaves and one more acting as a Master. They will be connected using SPI (with separate CS’s). The slaves will run A/D converters and the Master will request the data in blocks of 6 kBytes. I estimate that one block will require a few hundred milliseconds and that would be fast enough.

I have prototyped a system with two PSoC  5LP CY8CKIT - 059 Kits, one with an SPIM and one with an SPIS component. I have a UART on the Master to control it through a serial port on the PC and, for now, a UART on the Slave to help with debugging. The only other devices are an output pin on each to control the on board LED and an ISR on the slave board connected to the SPIS RX Interrupt (because I cannot figure out how to make the internal interrupt work).

I can send bytes from the Master to the Slave but have not succeeded in reading a block of bytes sent back by the Slave. I have pared the programs down to the bare minimum and include them here. (I hope the attach worked).

As you can see, I handle the UART in the the foreground and send a lower case b or v to blink the led or send  a version string for testing. If I send an upper case character to the Master, it sends, it via SPI, to the Slave.  That works and I can blink or output the version message on the Slave by sending  a B or V  to the Master. So my SPI interconnection does work. I am using a full duplex connection with both MOSI and MISO. For now, I do not have a CS, I just leave the Slave selected all the time.

But I have not succeeded in transferring a block of bytes back from the Slave. I make a small block (of letters to make the testing easier) and put them in a TX buffer in the Slave. (I made the Slave TX buffer 40 bytes long.) Then,when I clock any data in from the Master, the Slave sends them out on MISO. I can see them on my oscilloscope. But the Master does not read them properly.  It gets some correctly but not all. I am not sure when or how I can read them from the SPIM RX . I tried waiting for SPI done before reading the RX buffer. That put a few microseconds delay between transmitted bytes but still does not make it work properly.

Please answer the following questions

1. How do I make SPIM read the data that SPIS sends out

2. For SPIS internal Interrupt, what is the ISR name and how do I init it?

3. What is the difference between SPIS_WriteByte and SPIS_WriteTXData()

4. Does mode really matter if I am building both sides? Is one better?

5. Is this a sensible way to transfer a 6 kByte block? DMA is too complicated for me.

thanks

Dave

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4 Replies
dahec_263886
New Contributor

It appears that the source code for the Master did not get attached,  Here is another attempt.

Dave

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RyanZhao
Moderator
Moderator

Hi Dave,

CS of SPI must be controlled by master. If it is not, SPIS won't response master's clock.

If you want to remove CS of SPI, you have to control it by operate its control register.

Thanks,

Ryan

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RyanZhao
Moderator
Moderator

Hi Dave,

Have you tried the PSoC5LP code example, SPI_Design, integrated in PSoC Creator? If it can work?

Thanks,

Ryan

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dahec_263886
New Contributor

Ryan

Thanks, that helped a lot.  I had a look at that code example. I see that I just have to wait until all the transfers are done before testing for SPI Done (not after each byte). And I made the SPIM Rx buffer big enough to hold the entire packet.

Do you know if there is a complete project for this example or just the code? I would like to see how the components are configured.

Do you know how big a Tx or Rx buffer is reasonable. Is 6K too big or should I make a smaller buffer (100 bytes?) and shift the data in packets?

I would still appreciate any answers to my questions 2 - 5

Dave

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