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Hi,
I'm doing a PCB involving a CY8CKIT-059. The PSoC uses 2 Sequencing SAR ADCs (one with 8 differential channels, one with 4 single-ended channels), the USB component, a UART component, and multiple GPIOs. I'm also outputting 1.024V to a pin. I had to use the auto-assignment of pins because the analog iterative improvement did not converge when I manually assigned the pins.
Now, everything builds fine, but I get 107 notices that "Net_xxxx" is connected to one terminal only. Is this normal? What can I do to improve the design?
Also, concerning my routing of 1.024V to a pin, I get the warning "Voltage Reference Information: Vref '1.024V' is connected to terminal 'analog_0' of 'VREF_OUT' but no direct hardware connection exists." Will it work?
Thank you,
Fred
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PSoC 5LP
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Hi,
This will not cause any issues with the functionality. There is a mux before ADC to select between the internal and external reference. Since we are using only the internal reference, one input to the AMux will be left unconnected. Hence, it shows that analog signal is connected to only one terminal.
Functionality wise are you facing any issues with the results ? Will you able to share your project?
Best Regards,
Vasanth
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Hi,
This will not cause any issues with the functionality. There is a mux before ADC to select between the internal and external reference. Since we are using only the internal reference, one input to the AMux will be left unconnected. Hence, it shows that analog signal is connected to only one terminal.
Functionality wise are you facing any issues with the results ? Will you able to share your project?
Best Regards,
Vasanth
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Thank you, Vasanth.
I can't test right now as I don't have the hardware yet, I just wanted to make sure that the routing I used actually compiled well.
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Fred,
The sequencing SAR ADC component performs a application test to make sure there is only ONE analog connection from the assigned analog pin to the input of the mux. That's why it is reporting "Net_xxxx". Annoying isn't it? I ran into the exact same problem when I try to put more internal component inputs on the same analog line.
There must be a reason the Cypress engineer is making that a criteria. I'd like to know. (Anyone from Cypress willing to respond?)
My fix is to use an ADC component (SAR or Delta-sigma) and place and route my own AMux component in front of it. This is not as 'simplified' as the sequencing ADC but allows me more control and, of course, I need to establish my own code to synchronize the mux to the ADC conversions needed.
Len
"Engineering is an Art. The Art of Compromise."
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Thank you, Len