Gang,
I need to make a slave port, wereby the master (in this case PC/Linux) sends data (8 or 16, more later) to the PSOC3 which then streams this out I2S to a dac chip.
This PC/Linux machine has 2 ports available for me to do this:
1) IDE 16 bit parallel interface
2) Parallel Port with ECP/EPP capabilities
For ease of making this work, I am considering the ECP/EPP port since it is 8 bits wide and in ECP has DMA capabilities. The IDE works so similar so really here goes.
On a Write sequence to the PSOC3 there will be the following hardware setup (copied from http://www.beyondlogic.org/ecp/ecp.htm timming diagram there also):
1. Data is placed on Data lines by Host.
2. Host then indicates a Data Cycle will proceed by asserting HostAck.
3. Host indicates valid data by asserting HostClk low.
4. Peripheral sends its acknowledgment of valid data by asserting PeriphAck.
5. Host de-asserts HostClk high. +ve edge used to shift data into the Peripheral.
6. Peripheral sends it's acknowledgment of the byte via de-asserting PeriphAck.
~~~~~
Ok so say I transfer 512 bytes from the PC/Linux to the PSOC3. The problem I see is how do I know when the DMA transfer of each byte is done so I can indicate to the ECP port PeriphAck?
So I use the HostClk to indicate to the DMA that a transfer is required. But when do I know it read the port?
Same true with IDE if DMA or FIFO mode is used, how do I know the DMA read the port?
Or do I have to use the PLD functions to do this, some sort of latching then read?
Or is there some better way that I am missing?
Thanks
Gordon
