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PSoC 5, 3 & 1

Anonymous
Not applicable

Hi, 

   

is it possible to design a band stop filter with 50 hz on psoc using a filter block?

   

 

   

I tried but in pratical didn't work...

   

Thanks.

   

 

   

Regards,

   

Romil A.

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1 Solution
Bob_Marlowe
Expert II

Short answer: Yes!

   

Use the example project Filter ADC VDAC poll. Set sample frequency to 1 kHz, set Cutoff to 0.05 kHz, set gain to 0db.

   

Set ADC to use soc (start of conversion), and conversion mode to single-sample

   

Add a timer component to the sheet, set timer to UDB, 16 bits and period to get 1ms (1kHz)

   

Connect the timer tc to ADC soc signal.

   

This (untested) should work.

   

 

   

Bob

View solution in original post

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37 Replies
Bob_Marlowe
Expert II

Short answer: Yes!

   

Use the example project Filter ADC VDAC poll. Set sample frequency to 1 kHz, set Cutoff to 0.05 kHz, set gain to 0db.

   

Set ADC to use soc (start of conversion), and conversion mode to single-sample

   

Add a timer component to the sheet, set timer to UDB, 16 bits and period to get 1ms (1kHz)

   

Connect the timer tc to ADC soc signal.

   

This (untested) should work.

   

 

   

Bob

View solution in original post

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ETRO_SSN583
Esteemed Contributor

Something like this, attached.

   

 

   

You can set ADC for 16 bits, internal clock, 2000 sps, continuous.

   

See attched example project selector, start page of Creator, "find example project"

   

 

   

 

   

 

   

Regards, Dana.

Anonymous
Not applicable

i try yet this example. for frequency lower then  500 hz the block filter didn't work...

   

do you know why?

   

 

   

Regards,

   

Romil

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odissey1
Honored Contributor II
        Romil, DFB does not like low cut-off frequencies. But you can cheat DFB. Set it to filter cut-off 500Hz and input frequency 10kHz, but feed filter input with 1kHz sample rate. Then filter will provide you with 50Hz effective cut-off. This is kinda unfortunate, but DFB could have been improved in many ways.   
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Anonymous
Not applicable

i use the filter block and not DFB (digital filter block). 

   

I modify the "Filter ADC_VDAC" example such like dana said and used it for create a bandstop filter with fc=50Hz. 

   

 

   

Regards,

   

Romil a

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ETRO_SSN583
Esteemed Contributor

"DFB does not like low cut-off frequencies."

   

 

   

Not exactly. The problem at low frequencies, FIR, is pole locations proximity and the

   

precision they require. So LF FIR filters require very high order.

   

 

   

But in cascaded BiQuad this issue much less stringent. But the problem

   

here is BiQuads have problems with linear phase solutions. They are also

   

subject to oscillation and overflow if not carefully design due to feedback

   

architecture, unlike FIR. But forum worked with another customer who needed

   

a BP solution at 50 Hz. Keep in mind when working down here at Hz level

   

settling times of filters very very long. So if you are digitizing stuff you need

   

to factor that into the design.

   

 

   

Many design at VLF are floating point, the DFB is of course 24 bit fixed point.

   

Regarding the order needed to get pole/zero locations at precise locations.

   

 

   

Some alternative ways of getting at low freqs with effective computational

   

resources, attached.

   

 

   

https://www.dropbox.com/sh/mbjgmm7ed3fz7dk/AACLC2hYCk2rRCmYYN52zdMqa?dl=0

   

 

   

Regards, Dana.

Anonymous
Not applicable

i need to implement a notch filter(50 hz) using a digital filter but i the filter don't work with low frequency.

   

If any example about this kind of digital filter?

   

 

   

Regards Romil.

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ETRO_SSN583
Esteemed Contributor

I thought you already did this ?

   

 

   

i use the filter block and not DFB (digital filter block). 

   

I modify the "Filter ADC_VDAC" example such like dana said and used it for create a bandstop filter with fc=50Hz. 

   

 

   

Regards,

   

Romil a

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Anonymous
Not applicable

I attach the file about the filter 50hz

   

Check it please.

   

Regards,

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Bob_Marlowe
Expert II

You have to adjust your ADC conversion rate to 1.1 kHz as specified in the filter's sampling rate. Use a PWM with an appropiate period and enable your ADC for a start of conversion input and single conversion.

   

Modifications (untested) attached.

   

 

   

Bob

Anonymous
Not applicable

i can't test the zip-

   

This is error "This file would not be considered in the update process."

   

Thanks

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Bob_Marlowe
Expert II

Does this archive work? I'm using Creator 3.3

   

 

   

Bob

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Anonymous
Not applicable

i'm using creator 3.2 and the problem is same with the last attachment you put here

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Anonymous
Not applicable

if i open the cysch file the error is "Type System.Drawing.FontStyle, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a with Guid none was not found)" and now i tried on Creator 3.3

   

 

   

Regards

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Bob_Marlowe
Expert II

When all fails use the short description I gave and create the modifications yourself, It is just a 5 minute-job. Nonetheless I would suggest you to upgrade to Creator 3.3, there have been corrections made.

   

 

   

Bob

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Anonymous
Not applicable

i upgrade the software.

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Bob_Marlowe
Expert II

And? Did it work??

   

 

   

Bob

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Anonymous
Not applicable

yes. 50 hz work fine. but i have the other problem. if i put 200hz the output signal doesn't have correctly. the signal is something like stair...

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Bob_Marlowe
Expert II

Can you explain / post snapshots a bit more? 200 Hz where? Input to ADC??

   

 

   

Bob

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Anonymous
Not applicable

yes input ADC

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Bob_Marlowe
Expert II

Check the center frequency of the filter, could be set to 500Hz instead of 50Hz

   

 

   

Bob

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Anonymous
Not applicable

check attach 

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Bob_Marlowe
Expert II

I thought your settings of the filter were your required values. So

   

What is your input frequency range?

   

Any other restrictions?

   

 

   

Bob

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Anonymous
Not applicable

frequency range is 10-400hz.

   

regards

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Bob_Marlowe
Expert II

So you will need roughly a sample frequency of 10 to 20 times the upper frequency = 4 to 8kHz. You have to adjust that value in the filter block AND in the PWM generating the soc signal.

   

Example attached, BUT Forgot to adjust PWMClk to 600kHz. Please diys

Anonymous
Not applicable

 I tried and the example and the worked.

   

Thanks bob. 

   

is it possible to write the values on array?

   

i need to write the output values from filter on array.

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Bob_Marlowe
Expert II

You can easily store the values into a defined array instead or additionally to sending them to DAC. A bit more complicated but working (there are example projects on how2) would be to use DMA. Will save a lot of CPU power!

   

 

   

Bob

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Anonymous
Not applicable

ok. i will chek before test this filter. 

   

i have some question about program. why are you add 128u in this line "VDAC8_SetValue(Filter_Read8(Filter_CHANNEL_A) + 128u);"?

   

Regards

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Bob_Marlowe
Expert II

The result of the filter is an int8, so it has got a sign and values from -128 to +127. The ADC accepts uint8 only, so we need to offset the filter result by 128 to retrieve positive values only.

   

 

   

Bob

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Anonymous
Not applicable

ok bob

   

thanks.

   

I have a array with values and i need to filter this value using the  filter block. is it possible?

   

Regards.

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Bob_Marlowe
Expert II

So: You have got an array of values that you want to feed into the filter? Then you should setup a DMA and transfer the data directly into the filter. Since the information for the sample frequency is lost you will have to set that in the filter to get a reasonable result or trigger the DMA with a timer and simulate taking a sample.

   

 

   

Bob

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Anonymous
Not applicable

ok, thanks.

   

I try to configure two channel from filter block but the channel 2 didn't work.

   

I attach the code from DMA config i use.

   

Check it please

   

 

   

Thanks

   

Regards

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Bob_Marlowe
Expert II

Yes, you did not start the TD for channel B

   

CyDmaChSetInitialTd(channelHandle, tdChanA); // Starts channel A

   

You could try

   

CyDmaTdSetConfiguration(tdChanA, 1u, tdChanB 0u); // When TD for A is done, next channel is B

   

 

   

CyDmaTdSetAddress(tdChanb, LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEbH_PTR));

   

Shouldn't it be a capital "B" in "Filter_STAGEbH_PTR"??

   

I cannot check the other parameters because a .txt file does not work in the IDE, better upload the complete project!

   

 

   

Bob

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Anonymous
Not applicable

i attach the code.

   

check it please.

   

Thanks.

   

 

   

Regards.

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Bob_Marlowe
Expert II

Rom, probably you misunderstood me: I am talking about a project archive which I can open (after expanding) in Creator.

   

To build one, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.

   

 

   

Bob

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Anonymous
Not applicable

it is possible to open a case? i can't send you a entire file

   

thanks

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Bob_Marlowe
Expert II

You always may create a case.

   

 

   

Bob

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