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PSoC 5, 3 & 1

Anonymous
Not applicable

I can't seem to get a FIFO_FULL no matter how many writes I make to a shift register FIFO.  Since I control the LOAD signal, I'm fairly certain data should not be transferred out of the FIFO and yet it never fills up. 

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3 Replies
Anonymous
Not applicable

Hi rdaley,

   

 

   

Can you please tell us what is the size of FIFO you are using? Is it 4?

   

Are you reading the status of FIFO immediately after writing the maximum number of  values to the FIFO without loading it to the Shift Register?

   

 

   

Regards,

   

dasg

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Anonymous
Not applicable

The FIFO size is 4. I check to make sure the FIFO is not full then I write to the FIFO. The data is not transferred to the shift register until the FIFO is full.

   

while(ShiftReg_1_GetFIFOStatus(ShiftReg_1_IN_FIFO)!=ShiftReg_1_RET_FIFO_FULL)
        if(ShiftReg_1_WriteData(i)==CYRET_SUCCESS)
            success = 0x01;
        else
            success = 0x00;

   

As far as I can tell, GetFIFOStatus always returns FIFO_EMPTY, no matter how may writes I make.

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Anonymous
Not applicable

I've more info on this problem, in my case a ShiftRegister v2.30 Psoc3.3SP2, 25bit, left shift,  fifo length = 4:

   
CyDelayCycles(1); // StatusRegister = 0x18 => GetFIFOStatus = FIFO_EMPTY  for (counter = 0; counter < ShiftReg_SSI_FIFO_SIZE - 1; ++counter) {     ShiftReg_SSI_WriteData(counter<<1);         CyDelayCycles(1); // StatusRegister = 0x18 => GetFIFOStatus = FIFO_EMPTY  }   ShiftReg_SSI_WriteData(counter<<1); // fifo is FULL CyDelayCycles(1); // StatusRegister = 0x08 => GetFIFOStatus = FIFO_EMPTY  for (counter = 0; counter < ShiftReg_SSI_FIFO_SIZE - 1; ++counter) {     ActiveBuffer_Write(1); // load signal      ActiveBuffer_Write(0);     CyDelayCycles(1); // StatusRegister = 0x10 => GetFIFOStatus = FIFO_PARTIAL } ActiveBuffer_Write(1); // load signal      ActiveBuffer_Write(0); // fifo is EMPTY CyDelayCycles(1); // StatusRegister = 0x18 => GetFIFOStatus = FIFO_EMPTY 
   

But tryng to fill a partially filled fifo:

   
 CyDelayCycles(1); // fifo is EMPTY       for (counter = 0; counter < ShiftReg_SSI_FIFO_SIZE; ++counter) {     ShiftReg_SSI_WriteData(counter<<1);         CyDelayCycles(1); }   CyDelayCycles(1); // fifo is FULL : StatusRegister = 0x08 => GetFIFOStatus = FIFO_EMPTY ActiveBuffer_Write(1); // load one data, ActiveBuffer_Write(0);  CyDelayCycles(1); // now the fifo is partialli filled : StatusRegister = 0x10 => GetFIFOStatus = FIFO_PARTIAL ShiftReg_SSI_WriteData(counter<<1); // now the fifo is correctly FULL, with StatusRegister = 0x00 => GetFIFOStatus = FIFO_ FULL 
   

so in my case the GetFIFOStatus is completely useless, but also the status register seems useful only to detect fifo full ( == 0x08 || == 0x00)

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