Detection capsense problem

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
alma_284856
Level 3
Level 3
First like received

 Hi everyone,

   

I designed a board which contain 20 capsenses with a PSOC5LP CY8C5888LTI-LP097.

   

My problem is that when I touch one capsens like for example P0[2], several capsense P0[4],P0[1],P0[6],P0[7],P0[0] are activated also. It's like all the port 0[xx] is unsettle.  I don't understand why, I tryed to respect design rules, I put capacitors on VDDIO as you can see in my schematic. I use 2 channels for capsense, so I put two CMOD 1u capacitor as in the datasheet.

   

The weird thing is that capsense's tracks are not close on the PCB but the capsense is activated (see my PCB image). 

   

My track's width are 0.2mm with a cleareance of 0.19mm

   

 

   

So if you have any sugestions let me know

   

 

   

Thank you

0 Likes
3 Replies
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

Have you done the tuning using a bridge ?

   

 

   

    

   

          

   

http://www.cypress.com/?app=forum&id=2232&rID=53237     Miniprog3 as I2C Bridge

   

http://www.cypress.com/?rid=105688     CE95287 - CapSense CSD using Tuner with PSoC 3/5LP

   

http://www.cypress.com/?rID=58549     PSoC® 3 and PSoC® 5LP CapSense® Design Guide

   

 

   

 

   

Regards, Dana.

0 Likes
alma_284856
Level 3
Level 3
First like received

 Thank It's good now, the Resistor MOD was too big (1µF instead of some nF)

0 Likes
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

Thank It's good now, the Resistor MOD was too big (1µF instead of some nF)

   

 

   

should be

   

 

   

Thank It's good now, the Capacitor MOD was too big (1µF instead of some nF)

0 Likes