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Hi,
my question is the following. Is it possible to send the digital value of the deltasigma ADC directly to a digital comparator? By DMA or ...?
Thanks
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Svem_MZ,
Attached is a demo project showing DMA transfer from a 16-bit RAM buffer to the custom 16-bit Control Register. It utilizes custom component ControlReg16 (and a complimentaryStatusReg16) components which allow for simple DMA access. The ControlReg16 and StatusReg16 component are included into the project.
You can accommodate this project for DelSig_ADC to CReg16 transfer by changing DMA settings.
/odissey1
Figure 1. Project schematic. DMA transfers data from RAM buffer to CReg_1 on each Timer clock. When DMA transfer is complete, the program terminates.
Figure 2. UART Terminal output showing content of the Buffer, CReg_1 and SReg_1 registers.
Figure 3. Project annotation using PSoC Annotation Library v1.0
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Hi,
Peripheral to peripheral transfer should be possible. You can refer this example of using Delsig ADC and VDAC as a reference.
Additionally why are you planning to update the comparator ? If you tell what is the exact requirement we could suggest something better ?
Best Regards,
Vasanth
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Hi,
thanks for your answer.
I would like to compare the value from the ADC with some other values and link the results logically. This is of course also possible via software. Unfortunately, the example does not help, since the digital comparator always requires a connection at the inputs. When addressing via DMA, however, there is no connection from the DMA to the comperator.
Do you have some ideas???
Best regards
Sven
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Sven,
There are two easy ways to solve this.
Here's one that more closely matches your suggestion:
The ADC EOC causes a DMA from the ADC data registers to the CR_ADC control register. The CR_thresh register is used by you to set the threshold to trigger an event such as an interrupt. The Dcmp can be set to the threshold type you want.
Another way is to use a Voltage Fault detector component available on the PSoC5.
This allows for 1 to 32 analog inputs and it uses two VDACs and two analog comparators along with some UDB logic to determine one of three stages of each pin: Undervoltage, Good, and OverVoltage.
"Engineering is an Art. The Art of Compromise."
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Hi,
a question about your solution. Connecting 2 control registers to 16bit is possible, but how do I connect them to the comperator? Comparator with 16 bit is clear.Have you some ideas???
Best regards
Sven
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Sven,
Is this what you were asking about?
"Engineering is an Art. The Art of Compromise."
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Sven_MZ,
The DelSig-ADC is relatively slow, working in some kHz rate, so most appropriate technique would be using ADC interrupt and comparing the values in code. The other approaches could be justified only when working in MHz range, using SAR-ADC.
The SAR_ADC has digital output bus, which can be connected directly to the digital comparator. You can find a project using ADC_SAR_ex custom component (SAR_ADC modified with digital output bus) here:
ADC_SAR - Filter - VDAC streaming demo using DMA
Attached below is a demo project showing use of the ADC_SAR_ex output bus and digital comparator. The width of the output bus corresponds to ADC bit resolution.
Figure 1. Use of the ADC_SAR_ex digital output bus for digital comparator connection.
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/odissey1,
The ADC_SAR component you speak of is a custom component that has a standard SAR in the underlying schematic correct?
"Engineering is an Art. The Art of Compromise."
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Len,
The stock ADC_SAR has internal digital output bus, which is hidden. The custom ADC_SAR_ex simply brings that digital bus out for external use, for example digital comparator or FIFO. The custom modification is merely cosmetic (an output bus connector was added to the schematic), and the modified component maintains all the specs of the original ADC_SAR.
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Hi,
Thank you all😊. The suggestions help me a lot to solve my problem.👍
Best regards
Sven
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Svem_MZ,
Attached is a demo project showing DMA transfer from a 16-bit RAM buffer to the custom 16-bit Control Register. It utilizes custom component ControlReg16 (and a complimentaryStatusReg16) components which allow for simple DMA access. The ControlReg16 and StatusReg16 component are included into the project.
You can accommodate this project for DelSig_ADC to CReg16 transfer by changing DMA settings.
/odissey1
Figure 1. Project schematic. DMA transfers data from RAM buffer to CReg_1 on each Timer clock. When DMA transfer is complete, the program terminates.
Figure 2. UART Terminal output showing content of the Buffer, CReg_1 and SReg_1 registers.
Figure 3. Project annotation using PSoC Annotation Library v1.0
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I've been going over delta-sigma design concepts for a while and I want to try out an initial realistic design in Cadence Virtuoso. Some resources I've used have included books like the Schreier book and Baker's CMOS Mixed Signal Design.
Wondering if anyone here with some experience could suggest papers/references for specific delta-sigma ADC designs that could be appropriate for a first attempt?
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Hi,
Thank you all. There are lots of good tips here. And with your help I have now found a solution to my problem.
Best regards
Sven