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I am working with the latest version of the PSoC technical reference manuals.
PSoC® 5LP Registers TRM
(Technical Reference Manual)
Document Number. 001-82120 Rev. *G November 6, 2019
PSoC 5LP Architecture TRM
(Technical Reference Manual)
Document No. 001-78426 Rev. *G November 6, 2019
It looks compared to the previous versions the only change seems to be an added Infineon logo.
As a result, all page numbers are shift one page.
But even worse references to tables are misaligned in the Registers TRM
Now the reference from a bitfield points to the wrong table. This is very confusing.
Where can I find an explanation DSI fabric the information of the following registers is not very clear:
DSI[0..15]_HC[0..127]
DSI[0..15]_HV_L[0..15]
DSI[0..15]_HS[0..23]
DSI[0..15]_HV_R[0..15]
DSI[0..15]_DSIINP0 - DSI[0..15]_DSIINP5
DSI[0..15]_DSIOUTP0 - DSI[0..15]_DSIOUTP3
DSI[0..15]_DSIOUTT0 - DSI[0..15]_DSIOUTT5
DSI[0..15]_VS0 - DSI[0..15]_VS7
The documentation does not explain how peripherals and I/O pin connect the DSI.
Can you supply me with the correct documentation?
Best regards
Carl
Solved! Go to Solution.
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PSoC 5LP
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Hi Cava_4754561,
DSI provides an extensive fabric of programmable switches which connect signals within a UDB, between pairs of UDBs, throughout the array of UDBs, and between the UDB array and many other blocks in PSoC. When you draw a wire between a pin and a digital peripheral, PSoC Creator's cyfitter performs extensive complex computations to connect the appropriate programmable switches to connect the two points. We do not have a document explaining the DSI registers since it is complex and PSoC Creator helps you with the same. We also do not recommend to perform the DSI routings manually.
You can perform a connection in Toip Design and see the generated sources from Generated-Source/PSoC_5/cy_boot/cyfitter_cfg.c -> cyfitter_cfg(void) to see the registers configured for the connection.
Also, I could not find any issues with the table referencing in the document, the references were to the right pages. Could you please let me know which sections of the document you find issues? Please help me locate the issues with referencing. We will work on improving the document.
Regards,
Bragadeesh
Bragadeesh
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Hi Cava_4754561,
DSI provides an extensive fabric of programmable switches which connect signals within a UDB, between pairs of UDBs, throughout the array of UDBs, and between the UDB array and many other blocks in PSoC. When you draw a wire between a pin and a digital peripheral, PSoC Creator's cyfitter performs extensive complex computations to connect the appropriate programmable switches to connect the two points. We do not have a document explaining the DSI registers since it is complex and PSoC Creator helps you with the same. We also do not recommend to perform the DSI routings manually.
You can perform a connection in Toip Design and see the generated sources from Generated-Source/PSoC_5/cy_boot/cyfitter_cfg.c -> cyfitter_cfg(void) to see the registers configured for the connection.
Also, I could not find any issues with the table referencing in the document, the references were to the right pages. Could you please let me know which sections of the document you find issues? Please help me locate the issues with referencing. We will work on improving the document.
Regards,
Bragadeesh
Bragadeesh
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All pages are shifted one page and almost all tables are shifted one table.
E.g on page 1475
See Table 1-794.
But table describes another bit.
Table 1-794. Bit field encoding: FIFO_DYN_ENUM
Value Name
- 1'b0 STATIC
- 1'b1 DYNAMIC
Description
Default. FIFO direction is static and controlled by the associated Fx_INSEL bits (CFG15).
The associated FIFO direction is dynamically controlled by the associated 'dx_load' Datapath input signal. When the 'dx_load' signal is '0', the access is internal, where the FIFO is both a source for the Datapath, and a destination for the Datapath (destination path from Fx_INSEL bits). When the 'dx_load' signal is '1', the access is external, where the CPU can both write and read the FIFO. When dynamic mode is activated, the dx_- load signals are disabled for use as Data Register load signals.
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Carl,
As Bragadeesh indicated, using the Top Design to create a 'design-time' schematic of the logic you want to implement is the easiest and potentially more optimal method of working with the UDBs and DSI fabric in the PSoC.
Is there a specific reason that you want to modify the DSI routing at 'run-time'? Although theoretically possible, it's complicated and has its side-effects if not carefully thought out.
Len
"Engineering is an Art. The Art of Compromise."
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PSoC creator is a Windows only tool, only supports an old version C compiler. We need an open source toolchain for the PSoC.
I think the routing is only complicated because there is no good documentation, I have to reverse engineer the DSI fabric with the help of the description of the PSoC patents.
I do not need to change the DSI at run-time now.
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PSoC Creator's cyfitter performs extensive complex computations to connect the appropriate programmable switches to connect the two points. We do not have a document explaining the DSI registers since it is complex and PSoC Creator helps you with the same.
Can you supply me with the same documentation the Software engineer used to write the cyfitter tool. If it is so complex I can't imagine that he/she wrote the tool without any documentation.
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Hi Cava_4754561,
Unfortunately, we do not have any document explaining the DSI registers as they are expected to be taken care by the Creator itself.
However, we are checking with our software team if we can provide any customer facing document that explains these registers.
In the meantime, please let us know if you are looking for something more specific (such as design requirement) so that we can help you better.
I was able to find the error you mentioned in the document. I have filed a ticket internally to update the document.
Thank you for your interest with our products.
Regards,
Bragadeesh
Bragadeesh
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How can I get in contact with the software team. I am working on a cross platform (MacOS, Linux, Window) C++ API for low level / high level PSoC 5LP programming. I use C++ compiler features to make low level programming more readable.
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Hi Cava_4754561,
Our software team is internal to Infineon. We are checking with them for the relevant document if any. Please give us some time. I will get back to you once I hear from them. We appreciate your patience.
Regards,
Bragadeesh
Bragadeesh
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Bragadeesh,
Thank you for your reply.
Comment:
I do not get an e-mail when somebody reacts to this post. Where can I change the setting for this?
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Carl,
Strange. When I participate in a thread and especially if I initiate the thread (like you do here), I automatically get emails when something new is posted to it.
Make sure your profile here has your correct email address.
Also you may not have the proper notification settings.
Look at the very top of the post for your avatar (in your case it is the Robot). Select your avatar and then select "Preferences"
Next make the selections in the Preferences menu. Here's mine.
There are other settings not shown here.
Once you've set all the settings you want select "Save"
Len
"Engineering is an Art. The Art of Compromise."
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Hi Cava_4754561,
Unfortunately, we do not have a public documentation describing the internal architecture or the registers description of the DSI architecture. Considering the complications behind implementing DSI routing by direct register writes, the description of these registers is not made public.
After discussions with our software team, it is recommended that we should only use PSoC Creator to route these DSI signals and then extract the register configuration from the cyfitter output to be used with a different platform as suggested earlier.
Regards,
Bragadeesh
Bragadeesh
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Hi Carl,
I was looking for similar information recently and came across http://www.psoctools.org/ which has some details on DSI fabric switching and a few examples that may be useful to you.
Cheers, Phil.