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PSoC 5, 3 & 1

EuDr_2339226
New Contributor II

Hello everyone,

I was trying to work with digital design and did this:

2018-01-22.png

Does this configuration make any sense? It should be the equivalent of the following firmware solution:

for(i=0; i<N; i++){     //'N' is a quite bug number that

            TX1_Output_Write(key1);     //key1 is an array of ones and zeros

            j = ((j+1)%KEY_SIZE);         

}

According to 'Application Note_Digital Design Best Practices' I'm consuming one UDB of the 24 available for each Control Register I'm using. Is this right?

Would it be better to use a LUT instead?

The result I'm willing to acheive is a bit per bit wave shaping, like this:

WA000005.BMP

This is the result of the key1 array "scanned" N times by the for cycle listed before. Now I want to do the same with the schematic in the first picture, with a "more hardware" solution. Is it better a LUT or should I continue with the Control registers?

I'm looking forward for your answers and support.

Thank you all in advance.

Best regards,

Eugene

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1 Solution
Bob_Marlowe
Expert II

Just re-reading your question.

A UDB contains a conrolreg, a statusreg, 2 LUTs some more logic, a counter and a programmable ALU. So it will not matter much whether using an LUT or a control register.

Bob

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6 Replies
Bob_Marlowe
Expert II

Without checking the equivalence of the two solutions I can say: It is up to you whether to use software, hardware or both for the solution of a problem.

In your case you must keep in mind that a pure hardware solution frees the CPU so that it could perform other jobs in the meantime.

Bob

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EuDr_2339226
New Contributor II

Thank you for your answer Bob,

I know that Verilog maps to logic (UDBs) and C runs on the CPU, that's why I've done more versions of the same project.

I'll continue to wait for a more specific answer to my question.

Regards,

Eugene

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Bob_Marlowe
Expert II

Just re-reading your question.

A UDB contains a conrolreg, a statusreg, 2 LUTs some more logic, a counter and a programmable ALU. So it will not matter much whether using an LUT or a control register.

Bob

View solution in original post

EuDr_2339226
New Contributor II

@

Note: The PSoC Creator Control and Status Register Components can be configured as one to eight control outputs

or status inputs, as Figure 17 shows. Although it is possible to create multiple single Control or Status Components,

each Component uses an entire UDB register. A better method is to use Control or Status Components with multiple

outputs or inputs. This is especially true for status inputs which have a common clock.

As underlined I'm just using the whole register in the UDB and not the whole UDB, I had doubts on this!

Thank you very much, you were really helpful!

Credits to you dear Bob

Ciao,

Eugene

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Bob_Marlowe
Expert II

The LUTs are made using the PLDs (Programmable Logic Device)

Bob

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EuDr_2339226
New Contributor II

Yes Bob, I modified my last answer many times. I'm quite new to this platform and a lot to learn in electronics but I'm trying hard!

I read that few rows down the pdf.

A pleasure to co-op with you.

Tschuss,

Eugene

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