PSoC3/PSoC5 device has multiple sources which can reset the device.
Low Voltage Detect Analog, LVI-A
Low Voltage Detect Digital, LVI-D
Software Reset and so on
Once the device is reset it is possible to identify the source of reset by reading the value of the register, RESET_SR0. However this register is read on clear. When the reset is triggered and the device boots, the device by default waits for bootloader and in the bootloader code this register is read and the status is cleared. However before reading this register the code preserves this register value as a variable, uint8 CyResetStatus.
Immediatlet after Reset(due tp watchdog timer or software reset) you might read the RESET_SR0 and find that it is zero. By reading the variable CyResetStatus you will be able to identify the source of reset. You can find more about this in the system reference guide(Preservation of Reset Status (PSoC 3 and PSoC 5)).