I currently trying to bypass a digtial signal trough the PSoC5. I attached an image to clearify the configuration.
The pins 2 and 4 transfer the clock signal of an external BiSS interface which is set to 2 MHz and Pin 3 and 6 shall transfer data. Pin 2 and 3 are connected to an external Biss-Interace and pin 4 and 6 are connected to a sensor.
But it does not work. I can not set up a connection. My question is: What may causes the problem? Could the internals of the PSoC destroy the signal or slow down the clock signal?
I checked if bypassing is possible with analog pins and it worked.
easiest for us to find errors is always to have a complete project to look at all of your settings. Can you provide us with a project archive? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
I made some minor corrections regarding synchronization. I also changed the pins for IO and the debug interface.
Are you using a development kit like the CY8CKIT-050LP?
Keep in mind that your analog path resistance is ~750 Ohms. You can prove that by switching to analog view and using the ohm meter feature.
I did not see an analog path on your schematic, but if you do
these might help -
http://www.cypress.com/?rID=43337 AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations
http://www.cypress.com/?rID=57571 AN72382 - Using PSoC® 3 and PSoC 5LP GPIO Pins
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
I tested the digital output with a multimeter by changing one output pin every second and it worked
I tried a lot for enabling BiSS communication trough the PSoC, but nothing worked out. E.g. deactivating input buffer and set input pins from CMOS to LVTTL. I think the PSoC slows down the signal, which especially concerns the bypassed clock signal.
Eventually, I think it is not possible to bypass a BiSS signal with 2 MHz clock trough the PSoC.
Thanks to all,
Using a scope look at timing between data and clk before bypassing, and after.
If you need more delay in data, clock is not producing enough setup time, then use
a buffer to create some delay in either clk or data to get back to original measurements.
Be aware that the optimizer will take out redundant gates, so either shut it off or use more
complex gates , like XOR, to get delay.