Are those pins(40, 41, 57-62) any special in PSoC LP5

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yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Hello,

We are using PSoC LP5. I found in all our designs, pin 40, 41, and pin 57 --- pin62 are not connected to anything at all. I wonder why it is like that? Are those pins somewhat for special purpose?

Now we are short of GPIO pins, can we use some of those pins as GPIO?

Regards,

Yan

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1 Solution
MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Yan-san,

 

I understand that you are asking about 100-TQFP package of PSoC5LP.

These terminals (40, 41, 57 to 62) are NC and are not connected internally, so they cannot be used as GPIO.

The same goes for A1, A9, L1 and L9 in the WLCSP package.

MaMi_1205306_0-1660806493550.png

The reason is that the maximum GPIO of PSoC5L is 72 for both 100-TQFP and 98-WLCSP.

P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0], P12[7:0] and P15[7:0] total 72

MaMi_1205306_2-1660807322012.png

In other words, the above is the entire system of PSoC5LP.

 

Regards,

 

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4 Replies
MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Yan-san,

 

I understand that you are asking about 100-TQFP package of PSoC5LP.

These terminals (40, 41, 57 to 62) are NC and are not connected internally, so they cannot be used as GPIO.

The same goes for A1, A9, L1 and L9 in the WLCSP package.

MaMi_1205306_0-1660806493550.png

The reason is that the maximum GPIO of PSoC5L is 72 for both 100-TQFP and 98-WLCSP.

P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0], P12[7:0] and P15[7:0] total 72

MaMi_1205306_2-1660807322012.png

In other words, the above is the entire system of PSoC5LP.

 

Regards,

 

Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Yan,

How many more GPIO pins do you need?

You may have already done this but not everyone knows this:

If you set the DWR/Debug Select to GPIO this frees up the pins dedicated for assignment to GPIO.

Len_CONSULTRON_0-1660825493703.png

 

Len
"Engineering is an Art. The Art of Compromise."

Hi Len,

We need 3 more GPIOs. Do you mean by the settings you mentioned, the NC pins(40, 41, 57-62) can be changed to GPIOs?

Thanks,

Yan

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Yan,

As  posted those pins are not even connected inside the IC.  The maximum GPIO count for the PSoC5LP is 72.  The pins listed as NC are extra pins because the package uses is more than the IC die pins available.

When you set the DWR/Debug Select to GPIO then P1[0], P1[1], P1[3], P1[4] and P1[5] are available for GPIO use.  Setting other debug modes allocates some or all of these pins for debugging.

Len_CONSULTRON_0-1660840498335.png

The pic above is the pins allocated for debugging for the JTAG 5-pin mode.

Len
"Engineering is an Art. The Art of Compromise."