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PSoC 5, 3 & 1

dacx_4333566
New Contributor II

Good day,

I am newbie to PsoC. Recently, I am doing a project of improving impedance meter(original resources: Chris Keeser) which able to process with 0.01Hz frequency by using PSoC 5LP Developing Kit. The figures below shows the TopDesign analog circuit and digital circuit:

1.PNGAnalog Circuit

2.PNG

Digital Circuit

The frequencies were generated by using Divider(PWM) with the frequencies range 0.01Hz, 0.10Hz, 0.20Hz, 0.50Hz, 1.0Hz, 2.0Hz, 5.0Hz, 10.0Hz, 50.0Hz and 100.0Hz and the periods(in micro second) write into Divider are 250000, 25780, 12890, 5155, 2577, 1288, 515, 257, 51 and 25 respectively to the frequencies.

The problem discovered from the data sheet of Pulse Width Modulation was the range of period count can be wrote for the divider maximum for 16 bits wide resolution where the period assigned for 0.01Hz is 250000 which exceed the 16 bit wide range and the frequencies measured with oscilloscope showing the value x100Hz than the frequencies needed and waveform showing unstable at 100Hz.

Is there any suggestion for process the 0.01Hz to the circuit in another ways and solve the problems of generating correct frequencies?

Thank you.

Dawn

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1 Solution
Len_CONSULTRON
Honored Contributor II

Dawn,

Moto  and \odissey1 definitely have valid suggestions.

I'll provide another one for academic purposes.

As the clock to your PWM you are using the BUS_CLK directly.  This clock is the most efficient for allocating clock resources on the PSoC.

However if you change to using either "Auto" or "MASTER_CLK" instead, you can use a digital clock resource which has a 16 bit divider available for control of the input clock to your 16-bit PWM.  Together, you get a combined 32bits of division available to your application.

You already know how to change the PWM period.  To change the incoming clock divider just use:

Clock_SetDivider(uint16 clkDivider)  where clkDivider is the desired divider + 1.

pastedImage_3.png

Len

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

6 Replies
MotooTanaka
Esteemed Contributor

Hi,

I wonder if you can use Timer, which can have up to 32bit counter.

000_Timer_25MHz.JPG

If you need 50% duty clock, adding a TFF may take care of it, with the divider/2.

000_with_tff.JPG

Divider value 250000

001_div_2500000.JPG

Divider value 25

002_div_25.JPG

moto

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MotooTanaka
Esteemed Contributor

Hi,

I recalculate the math (elementary school level?).

If all you need is 0.01Hz to 100Hz, we may use 24bit Timer.

If I can provide 24KHz clock to the timer, like

011-schematc_24kHz.JPG

If divider is 2400000, freq is 0.01Hz (period = 100s)

012-0_01Hz.JPG

If divider is 240, freq = 100Hz (period = 10ms)

012-schematic_100Hz.JPG

moto

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odissey1
Honored Contributor II

Dawn,

To get higher frequency range you can use DDS24 or DDS32 community components instead of PWM

DDS24: 24-bit DDS arbitrary frequency generator component

which provide 24-bit and 32-bit frequency range accordingly. As a bonus, unlike the PWM, with DDS you can directly set any frequency.

/odissey1

Len_CONSULTRON
Honored Contributor II

Dawn,

Moto  and \odissey1 definitely have valid suggestions.

I'll provide another one for academic purposes.

As the clock to your PWM you are using the BUS_CLK directly.  This clock is the most efficient for allocating clock resources on the PSoC.

However if you change to using either "Auto" or "MASTER_CLK" instead, you can use a digital clock resource which has a 16 bit divider available for control of the input clock to your 16-bit PWM.  Together, you get a combined 32bits of division available to your application.

You already know how to change the PWM period.  To change the incoming clock divider just use:

Clock_SetDivider(uint16 clkDivider)  where clkDivider is the desired divider + 1.

pastedImage_3.png

Len

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

NoriakiT_91
Employee

I'll provide yet another one.

If you want to get a high division ratio divider,  It is easy to cascade multiple dividers.

GS001061.png

Because the propagation delay from the "en" input to "div" output cannot be ignored, the "div" output is synchronized with the "clk" input.

GS001062.png

If you want a 50% duty clock output, please use a TFF at the last stage.

This prescaler implementation is a part of my frequency counter.  Please refer following repository for the project.

GitHub - noritan/Design275: Frequency counter revised - "CY8C3866AXI-040" on "CY8CKIT-030"

You can also see a BLOG article in Japanese.

Regards,

Noriaki

dacx_4333566
New Contributor II

Thank you for all suggestion and recommendation from all of you, it's helpful and I learned a lot.

Dawn.