If the routing is getting completed and project builds fine, PSoC is expected to work properly. Regarding the routing iterations and additional time taken, it can be due to the complexity of your design or some pin selection which makes the system difficult to route with routing resources available. You can always see CYDWR-> Analog tab and see how the routing is done. Also check the I/O pin selection section in Hardware Design Guide. This will help you to select the right pins for your purpose. Also see analog internal routing considerations. Additionally Pin selection for analog designs application note will be also helpful.