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PSoC™ 5, 3 & 1

chmi_4559946
New Contributor

I create a project for the Psoc 5LP,when build the project,the output window displaying the ifno as below:

Analog Placement...

Info: apr.M0002: Analog signal "Net_10043" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10044" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10045" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10046" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10047" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10048" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10049" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10050" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10051" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10026" is connected to one terminal only. (App=cydsfit)

Info: apr.M0002: Analog signal "Net_10129" is connected to one terminal only. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 35% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 52% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 86% done. (App=cydsfit)

Analog Routing...

Log: apr.M0019: The analog placement iterative improvement phase is beginning. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 6% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 13% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 20% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 26% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 33% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 40% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 47% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 53% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 60% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 67% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 74% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 80% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 87% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 94% done. (App=cydsfit)

Log: apr.M0019: The analog placement iterative improvement phase is beginning. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 6% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 12% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 19% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 25% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 32% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 38% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 44% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 51% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 57% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 64% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 70% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 76% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 83% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 89% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 96% done. (App=cydsfit)

Log: apr.M0019: The analog placement iterative improvement phase is beginning. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 6% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 12% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 18% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 24% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 30% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 36% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 42% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 48% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 54% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 60% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 66% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 72% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 78% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 84% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 90% done. (App=cydsfit)

Log: apr.M0058: The analog placement iterative improvement is 96% done. (App=cydsfit)

Analog Code Generation...

Info: apr.M0060: Comparator 'Comparator[1]@[FFB(Comparator,1)]' is powered up by analog subsystem to support an auto-enabled vref. (App=cydsfit)

Digital Placement...

Digital Routing...

I worry about the analog MCU pins can work well, pls help me to figure out this problem ,thank you very much !

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1 Solution
Vasanth
Moderator
Moderator

Hi Chen,

If the routing is getting completed and project builds fine, PSoC is expected to work properly. Regarding the routing iterations and additional time taken, it can be due to the complexity of your design or some pin selection which makes the system difficult to route with routing resources available. You can always see CYDWR-> Analog tab and see how the routing is done. Also check the I/O pin selection section in Hardware Design Guide. This will help you to select the right pins for your purpose. Also see analog internal routing considerations. Additionally Pin selection for analog designs application note will be also helpful.

Best Regards,
Vasanth

View solution in original post

2 Replies
Vasanth
Moderator
Moderator

Hi Chen,

If the routing is getting completed and project builds fine, PSoC is expected to work properly. Regarding the routing iterations and additional time taken, it can be due to the complexity of your design or some pin selection which makes the system difficult to route with routing resources available. You can always see CYDWR-> Analog tab and see how the routing is done. Also check the I/O pin selection section in Hardware Design Guide. This will help you to select the right pins for your purpose. Also see analog internal routing considerations. Additionally Pin selection for analog designs application note will be also helpful.

Best Regards,
Vasanth

View solution in original post

chmi_4559946
New Contributor

Hi Vasanth,

    Thanks for your very useful info, I studied the docs you recommened. I will optimize the Pin configuaration. Thank you very much.

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