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PSoC™ 5, 3 & 1

Anonymous
Not applicable

I am in the process of designing an SDR primarily targeted towards Radio Astronomy, sat com, and other very weak signals. The idea is to build an HF direct sampling receiver with a 210/MSPS 16bit ADC pipe, that can decimate down to 1MSPS, and then mix 400-415mhz and 1-2ghz down to HF. Im pretty confident as far as the RF design and most of the hardware goes but I haven't really done DSP code. I just ordered an Analog Devices Pluto SDR, which uses a Zynq as its main dsp/cpu, and am excited to play with that because I no nothing about FPGA, im not even sure if I want one in my project.

   

Anyways I have a few PSoC4 and 5 kits around, and I started thinking the PSoC5 has a 1MSPS ADC, and a bunch of other cool blocks to play with. I bought a bunch of the PSoC4/5 kits along with a Pioneer a while back because they looked pretty darn cool, and seem highly capable of building nice test and measurement tools. I ended up never using them because SDR and RF/Microwave projects took over all the other stuff I wanted to do. So I really don't know much about programming these chips at all! Luckily I bought "PSoC5 LP Measurement Projects" on Amazon, and Cypress has a ton of cool resources. Im also not a newb when it comes to programming micros in C or making schematics :)!

   

So I think maybe a miniature SDR project is a good place to start, before I throw all these expensive ADCs, and RF components on to a PCB and end up picking something for DSP and Data Transfer on a Whim and the put it together and realize I hate it because I had no idea what I needed at the time. I don't have any receivers digital or analog that receive Super/Very/Extra Low Frequency, not only are they neat for listening to submarine communications and standard time signals around the world, but a lot of solar astronomy uses VLF.

   

So my idea is that I can connect an active whip antenna meant for 0-1mhz to the ADC, and then hopefully duplicate the signal in to an I and Q then shift the Q by 90 degrees using all hardware blocks. From there I can hopefully implement any decimation. filtering and modulation in the cpu, along with generating an FFT plot, maybe im asking to much of the micro... Since we are only sampling 1MSPS and we only care about 5Khz of the sample after that, I would assume the Hi Speed USB (12Mbit right?) should be fast enough to stream the IQ samples to the PC along with FFT plot data. I know making an FFT on the chip and sending it to the PC along with the IQ samples seems pointless, but I like the fact you can do things really fast an easy by piping the FFT points in to something like GnuPlot or Excel... that may be all the info you need sometimes.

   

So does this project seem feasible, or am I asking to much of the PSoC chip? Should there be enough digital blocks to at least do the IQ mixing? Not knowing much about CPLD or FPGA, im always curious just how big of a chip I would need to pick for a real SDR like the one I have in mind. I am actually kind of hoping when I build the bigger one that I may be able to do a lot of actual DSP on something like a ~200mhz+ micro or CPU like an xmos or cheap all winner a10 and then stuff a cypress usb3fx or gigabit ethernet controller on the SDR to get the data to the PC.

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odissey1
Honored Contributor II

robert,

I apologize for PSoC forums being completely screwed by the latest update. You may find several threads discussing SDR radio projects. See liks below:

https://community.cypress.com/thread/22792

Simple Radios

Attached are description of the SDR radio using Tayloe detector and PSoC3 (PDF and project code). With small effort it can be ported to PSoC5. The project can be greatly simplified if using external DDS chip to produce carrier frequency.

While working with PSoC micro is a lot of fan, I am sure that you familiar with low-cost RTL-SDR usb dongle (http://www.rtl-sdr.com/ ) and various downconverters for it to cover 0-20 MHz range. This might be a safe alternative if you want to get down to the root by skipping the hardware design fun.

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