PSoC™ 4 Forum Discussions

My ADC is running at 12MHz, it samples 5 channels and the actual sampling rate is 100KHz.

I just noted that reading a single channel using the ADC_GetResult16() command takes a whooping 1us at 48MHz CPU speed.

It takes over 5us to read the 5 channels. Now at 100KHz sampling rate, time between two successive samples is 10us out of which 5us is wasted in simply reading the ADC. Only 5 remains for performing other calculations before the next sample arrives.

This is very very slow. In fact what sense does it make if the ADC runs at 1MSPS and takes another 1us to read the channel.

Is there a faster method to read the ADC channels?

Can't we directly read the channel resistors?

Thanks

I have an ISR component ISR_1 connected to the OV pin of a PWM block.

In the main file I have the following code:

CY_ISR_PROTO(MyISR);
CY_ISR(MyISR)
{
    PWM_1_Stop();
}

int main()
{

    PWM_1_Start();
    ISR_1_StartEx(MyISR);
    CyGlobalIntEnable;
}

PWM should stop as soon as the interrupt is executed. But it does not.

Please help

Hey, I'm trying to boot a hack I found at Hackster.io for a sound generator starting from an IDAC. The project's main.c uses some TimerTick functions that get marked as errors when I build the program as, i.e., TimerTick_StartEx();

I'm using Creator 3.3 and a CY8CKIT-043 board, where can I find the related block or, in case it has changed, the equivalent functions? Maybe who wrote the code was a using a different Creator version. 

Regards!

Hello,

I am having an issue with using the UDB PWM component with 48 MHz HFCLK clocking. Since I was using the USB component, I must set the HFCLK to 48 MHz. When building the project, this warning message apperars:

Warning-1366: Setup time violation found in a path from clock ( clk1m ) to clock ( clkphase ).

And it indicates the max frequency being only 29.8 MHz.

Thanks for your help!

I have attached the project to this post.

Hello everybody,

we are currently evaluating the possibility to enhance our products with a BLE interface. We want to use a CYBLE-022001-00 for this. I am trying to get a firmware on the module via our main processor (EFM32GG). I used the AN84858 application note as a template for my project (http://www.cypress.com/documentation/application-notes/an84858-psoc-4-programming-using-external-microcontroller-hssp?source=search&keywords=an84858).

The MCU is connected with the 5-pin debug port on the evaluation board of the EZ-BLE. When  the module is preprogrammed with the PsoC Creator I can easily update the module´s firmware with a heximage from my board. If the flash is erased/ the module is new my code fails in the DeviceAcquire() function. Right after the setting the IMO to 48MHz the PollSromStatus() returns an error. It fails at reading the suitable CPUSS_SYSREQ value.

I´m only comfortable with programming the EFM32 family yet, so I might have overlooked some details. Maybe someone has an idea.

Thanks and greetings from Berlin

Hi,

I have a very big problem with DeepSleep in my project.

I use the CY8CKIT-042-BLE with the CY8CKIT-043A device. I have a very big project with an SPI-RTC, an SPI-LCD-Display, an adc, an Op-Amp, a timer, a reset-watchdog and of course the BLE-Component.

The RTC generates an interrupt each second and triggers the adc to do a measurement. Beside that a timer-component generates a 40ms-Interrupt for the handling of the BLE. Thats o.k. It works perfect if I use the "Sleep" mode.

I used the Global-Signal component with the "AllPortInt" and a custom ISR to wake up the device from the GPIO-Interrupt from the external RTC.

If I try to use the "DeepSleep" according to the example, I see that the device wakes up one time and then it is stuck in an endless loop. In the picture I added you see that the DeepSleep is entered (first signal goes low). It is interrupted by the BLE-component for some milliseconds. But if the RTC triggers (falling edge) the DeepSleep is left and never entered again. At 5.5s it looks like the AllPortInt triggers again, but I don't know why. I clear the interrupt in the ISR by calling _ClearPending() in both, the single GPIO-ISR and the AllPortInt-ISR.
This is the call stack from this situation:

0 CySysPmSleep() .\Generated_Source\PSoC4\cyPm.c 52 0x0000874A (All)
1 ll_exit_low_power_mode() ?????? ?????? 0x0000DC06 (All)
2 ll_task_handler() ?????? ?????? 0x000112C8 (All)
3 llft_service_queue() ?????? ?????? 0x00011AAE (All)
4 llf_task_start_routine() ?????? ?????? 0x00011A06 (All)
5 CyBle_StackTaskHandler() ?????? ?????? 0x0000C3E6 (All)
6 OS_scheduler() ?????? ?????? 0x0000D276 (All)
7 CyBleStackMgr_ProcessBleEvents() ?????? ?????? 0x0000C116 (All)
8 CyBle_ProcessEvents() ?????? ?????? 0x0000BE38 (All)
9 main() .\main.c 98 0x00000444 (All)

I have no clue what I should do now?
I hope that anybody can help me!

Thanks Andreas

Hi All,

I am using SPI & UART in my project,

Initially i added  UART(v2.50) into my project , works everything as expected.

Later i added SPI Master Fullduplex macro  and getting this below error.

Pin guidance unavailable: Resource limit: Maximum number of Macrocells exceeded (max=32, needed=37).

If i add the originlal SPI Master (v2.50) aslo im getting same error

please provide me the solutions

Thanks,

Ashok R

​Reading data at low addresses changes depending on when I read it.

How big is the RAM overlay? I assume it is for the interrupt vector table and that the table can not be in Flash.

I'm trying to calculate a CRC on the firmware during initialization and also later while it is running.