PSoC™ 4 Forum Discussions
Hi Guys,
I want to debug WDT Reset issues on Cypress PSoC 4200 BLE device I am using. I want to know that when there is a Watchdog time out reset which occurs, is there any way to know ARM M0 registers ?
Basically I want to know the contents of SP, LR and PC is that possible ?
If it is not possible how do we debug Watch dog timeout reset issues ?
Show LessI am using CY8C4125PVS-482Z for waterproof cap touch button design. It is a single button. The button width and length is 11mm. Cypress cap touch design guide specify that the button to guard clearance should be at lease 10mm and the guard thickness should be 2mm. Because our cap touch button has limited size. Can we reduce the button to guard clearance and reduce the guard thickness. Please recommend a minimum button to guard clearance and minimum guard thickness. Besides, Can we remove the outer shield surrounding the guard ring to reduce the size. What is the negative effect by removing outer shield
Show LessCan Cypress please provide the following properties for the LIN 2.1 interface on PSoC4S Plus??
How many elementary parts is the bit divided? |
How many bit-samples do you use? |
What is the sampling point position? |
What is the rule to decide the bit level? |
From the documentation, i found this recommended layer stackup:
1. Cap sensors
2. Sense traces
3. Hatched ground plane
4. PSOC and non-capsense related traces
My question is this - should layer 2 have a ground plane around the sense traces, or should layer 2 consist of ONLY the sense traces, and no other copper?
Show LessHi, I'm working on a design using the CY8C4245AXI-483 (44-TQFP) , with most pins being used as touch-sensors. I've noticed that two of the pins (P1[0] (pin 37) and P1[1] (pin 38) seem to be quite a bit less sensitive than the other pins (they all go to the same-size copper electrodes). I had to increase the bit count from 10 to 12 and reduce the threshold from 80 to 20 in order to get the same 'touchiness'. Is there anything unique or different about these 2 pins? I did notice that they are also Op-Amp inputs, could this be a factor?
Thanks in advance...
-Michael
Show LessAre there any examples of determining external battery level based on resources available inside a PSoC?
The BLE_Battery_Level example offers a method to charge an external capacitor with VRef then read it back on a different pin into the ADC. That requires an external component on Vref, which is already there, but also an external connection between Vref and a GPIO pin,
Greg.
Show LessHi,
I am using PSoC 4 CYBLE-214009. I am looking for a way to have UART "Wake up from deep sleep" enabled at the same time get interrupts generated from three pins on the same port.
Normally this is not supported, if I try to do it PSoC creator throws an error. However my idea is to modify the generated source or the UART IRQ to add the three pins to the mask. Such that if any of the pins or the UART go low then the UART ISR will get called and in there I can figure out the true source of the interrupt.
Does anyone know if this is possible? If so any guidance on the implementation is much appreciated.
Regards
MB
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