PSoC™ 4 Forum Discussions
There are many inconveniences because the number of collected data that can be stored in BCP is limited to 10,000.
If you look at the attached image file, you can see the outliers in the actual data on a graph, but it cannot be saved and analyzed.
Regarding some inquiries, it is said that the problem has already been forwarded to the SW team.
Why isn't an improved version released?
Why is data stored only after it is collected? You can just save the data as a file right away...
We ask for a quick resolution.
Show Less在电脑上连接板子和下载器后,板子无法供电,测试后发现Miniprog3的VTARG端的电压不足1V,请问这是什么原因,连接都正常,还有就是PSOC Creator怎么生成HEX文件
Dear Sirs and Madams,
We have a question about ExtClk clock settings in Bootloader project.
We are using CY8C4024AZI-S403 device with a UART Bootloader configuration in PSoC Creator 4.4 IDE.
In order to improve the clock accuracy of UART communication, The system clock is running with ExtClk.
When receiving a firmware update command from UART, the Bootloader is started by calling the Bootloadable_Load() API.
We have confirmed that the firmware update can be completed successfully if the Bootloader clock resource is IMO.
< Bootloader project clock settings : IMO >
However, firmware updates will not work properly if the Bootloader clock resource is set to ExtClk.
< Bootloader project clock settings : ExtClk >
*Note 1: Both projects correctly assign Bootloader.hex to Dependency of Bootloadble.
Is it not possible to set the Bootloader clock resource to ExtClk in the UART Bootloader of PSoC4000S?
Since clock accuracy between target of PSoC4000S and the host is important for UART communication, We are considering using ExtClk instead of IMO.
Regards,
Show LessHello,
I am trying to build a variable frequency drive by following this reference board REF-MHA1KIM5PSOC4.
The schematic and all other details are provided however its cannot find its code.
Can someone please share the code for this board?
Thanks
Show LessI am querying the register address and value of chip id of products CY8C4046FNI-T412T and CY8C4046FNI-T452EST, I do not know whether I have searched correctly.
The register address for chip id we found in the 400T series specification is 0x0FFFF144. Is the chip id address of the 400T series the same?
The corresponding register values are shown in the following two pictures.
I hope someone can help with that. Thank you very much.
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The PSOC creator version used was 4.4. The creation project discovered that there was no CY8C4025LQI-T411 model. May I ask how to solve it? thanks
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/PSoC-4/PSOC-creator-%E6%B2%A1%E6%89%BE%E5%88%B0CY8C4025LQI-T411/td-p/652629
Show LessDear Sir,
We saw the PSoC4700 inductive could support up to 16-channel inductive sensing.
I tried to use the PSoC creator to build up the solution but the MagSense Lx is limited to assign on Port 2 8pins only.
How to make a 16pins inductive solution?
Best Regards,
Billy
I want to do the following:
1. Send a 6 byte command to an SD card over SPI, interrupt on TX Empty (when command is fully moved out of the FIFO)
2. In ISR, empty the receive FIFO with either SCB_SpiUartClearRxBuffer() or reading the bytes.
3. Send dummy byte 0xFF, interrupt on TX empty, read RX byte, until a non-0xFF value is received (response from SD card).
So, assuming the SD Card responds on the second dummy byte after the command, I should see a total of 3 dummy bytes transmitted after the command. But, I am instead seeing 8, both in code and on a logic analyzer trace:
Using the debugger I have narrowed down the problem to this part in the ISR:
Bus trace when that breakpoint is hit (SCB is automatically de-asserting CS due to debugger pause):
Step 2 above is lines 51-54, Step 3 is the rest. Even though I have read all bytes out of the RX buffer, or used ClearRxBuffer(), after transmitting another byte, the RX buffer size reads 5, even though it was previously 0 to break out of the do/while loop!
Why? If I read all the RX bytes out of the FIFO/buffer, then transmit one more byte, why are there 5 bytes still sitting in the receive buffer? Those 5 plus the 3 dummy bytes = 8 extra bytes transmitted before the response byte is read from the FIFO.
I think the issue may be due to the TX Empty interrupt firing directly after I write a 0xFF to the TX buffer, since empty triggers when the last FIFO element is moved from the FIFO to the shifter. For example maybe the empty interrupt is firing more than once? Is there a better way to do a single byte transmit/check response, without the SCB automatically de-asserting CS (i.e. without SPI_DONE interrupt)?
I have attached the project, it targets the CY8CKIT046 with an SD module connected to the SCB through the PMOD header (port 6).
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