PSoC™ 4 Forum Discussions

Hi,

To get PSoC 4200 series supported with Daplink + pyocd, we need a "pack file" for it.

I'm told that psoc creator has a way to generate this, but need some guidance how to do it.

CMSIS-Pack documentation: https://arm-software.github.io/CMSIS_5/Pack/html/index.html

- .pdsc file format (XML): https://arm-software.github.io/CMSIS_5/Pack/html/packFormat.html

- Debug sequences: https://arm-software.github.io/CMSIS_5/Pack/html/debug_description.html

- Flash algo: https://arm-software.github.io/CMSIS_5/Pack/html/flashAlgorithm.html

thanks

David

related topic:PSoC 4 + Daplink / PyOCD?

In 2017 my company manufactured 5000 adapters using the CYBLE-022001-00, EZ-BLE chip and now we are in the process of manufacturing 4000 more and have a very tight deadline.

But we have a serious issue with the programming of the chip using the MiniProg3 Programmer Rev B. We can program the 2017 chips but not the current ones. The programmer says it can’t acquire the chip. We swapped the chips between a 2017 adapter board and a current board and confirmed that it’s the current Cypress BLE chip that is the issue (old chip programs fine on the new board, new chip does not program on the old board).

The visual difference between the old and new chips is that the new one has the following below the IC number

AMATEL:

06800-19-11443

Both have the same device id (CYBLE-22001-00) and  on the green portion R-005-101007.

Sure would appreciate any help anyone can give. We need to start the programming next week.

Thanks,

Mark.

I wanted to achieve only with a meter range advertising as peripheral device and mobile as central how can we achieve this..?

I am using cyble22201-01.

Hello,

Cortex M0 + can be set in ROM by the VTOR register.

Normally, it is set in RAM as follows by initialize_psoc () of Cm0plusStart.c.

CYREG_CM0P_VTOR = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM

The above process is set to ROM (address: 0x0), which is the initial value of Cortex M0 +, without this process.

In this case, the vector table is allocated to ROM, but is there any particular effect on the interrupts used by CapSense or EZI2C?

Thanks

Hi,

I came across the method to implement the capacitive touch using spring as a capsense sensor.

Can I get the any reference document to select the spring specification such as spring dimeter, spring height, thickness of metal spring, turns in spring.... and how it basically affect sensitivity.

I want to achieve sensitivity over 7mm thickness(4mm overlay + 3mm spacer) with around 12mm sensor area & 5mm distance between two sensors. There are multiple sensors on same board.

recommendation for selection criteria of spring would be highly appreciated.

Thanks in advance.

Hi All,

I'm using the PSoC4100SP with PSoc Creator 4.2.

I have to use the __LDREXW, __STREXW, __DMB.

I found these functions in cmsis.armcc.h, cmsis_hcc.h but I think the macro should be defined correctly.

Please let me know how to use it.

(Add)

Actually, I'm converting other mcu firmware to PSoC.

please refer to below.

int mxc_get_lock(uint32_t *lock, uint32_t value)

{

    do {

        // Return if the lock is taken by a different thread

        if (__LDREXW((volatile unsigned long *)lock) != 0) {

            return E_BUSY;

        }

        // Attempt to take the lock

    } while (__STREXW(value, (volatile unsigned long *)lock) != 0);

    // Do not start any other memory access until memory barrier is complete

    __DMB();

    return E_NO_ERROR;

}

Thanks and Regards,

YS

Hello,

Let me confirm the difference between the TRM initialization procedure of SCB (UART and SPI) and the automatically generated code from PSoC Creator.

- PSoC 4100/4200 Family PSoC 4 Architecture TRM (Doc No: 001-85634 Rev. *H)

- SCB Component v4.0

What are the possible negative consequences of not clearing and freezing the FIFO? My customer is concerned.

The TRM explains as follows.

=================================

15.3.6 Enabling and Initializing UART

The UART must be programmed in the following order:

3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-11.

a. Set the trigger level.

b. Clear the transmitter and receiver FIFO and Shift registers.

c. Freeze the TX and RX FIFOs.

=================================

15.2.6 Enabling and Initializing SPI

The SPI must be programmed in the following order:

3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-5:

a. Set the trigger level.

b. Clear the transmitter and receiver FIFO and Shift registers.

c. Freeze the TX and RX FIFO.

=================================

The SCB_Init() API calls SCB_UartInit() and SCB_SPIInit(). In the following, step 3a is processed, but it seems that step 3b and 3c are not processed.

SCB_UartInit() {

        ....

        SCB_RX_FIFO_CTRL_REG = SCB_UART_DEFAULT_RX_FIFO_CTRL;

        SCB_TX_FIFO_CTRL_REG = SCB_UART_DEFAULT_TX_FIFO_CTRL;

        ....

}

SCB_SPIInit() {

        ....

        SCB_RX_FIFO_CTRL_REG = SCB_SPI_DEFAULT_RX_FIFO_CTRL;

        SCB_TX_FIFO_CTRL_REG = SCB_SPI_DEFAULT_TX_FIFO_CTRL;

        ....

}

Thanks.