PSoC™ 4 Forum Discussions

setup :

SCB  I2C   slave  and SCB I2C  Master  examples

Master send  3 bytes []  and  Slave  return 3bytes   which  status reg update  after master is write 

in Master example  implement  with Delay CyDelay(CMD_TO_CMD_DELAY)

dialog da14531    write and read  at once  two bytes 

dialog da14531  write 3  bytes 1 reg address  and 2 bytes  data

CY8CKIT-046  update  readbuffer   2 bytes of  data 

from  what reason need delay in master ?  

problem :  when  dialog da14531 read  from  CY8CKIT-046   we need  double reading  

i trying  working  with ST microcontroller  not able  preproduce  the double reading issue 

any suggestion how correct write to slave  and  how slave update readbuffer correctly 

My Project is BLE with Fixed stack bootloader:   CYBLE-224116-01  Silicon: 1A6F, Family: AA, Major/Minor Rev: AC

Bootloader and Bootloadable component version is 1.60

Some boards program fine. Others, once OTA upgraded successfully, are then is stuck in a boot loop.  You cannot attach a debugger because it is not stable enough to get the device ID. 

Using PSoc Programmer, the .HEX files read from the two devices are identical. 

What could be wrong? 

Hi everyone

I am trying to count milliseconds in a project, but I don´t know how to adjust the parameters.  I attach the scheme of this part of my project.

uint32 counter_ms=0;

CY_ISR(TC_InterruptHandler){
//Clears the timer terminal count interrupt//
Timer_ClearInterrupt(Timer_INTR_MASK_TC);
counter_ms++;
}

int main(){

CyGlobalIntEnable;

Timer_Start();
TC_Interrupt_StartEx(TC_InterruptHandler);

}

Hello, thanks to supporting me,

I Program a CY8C4014LQI-421  (PSOC 4) with the PSOC programmer and PSOC miniprog3 and the target device was not well choosen. The target indicated was CY8C3666AXI-037T (PSOC 3) .

I did not see the difference using the target card, software response is correct .

Could you precise to me if the target device influence the programming in this case ?

NB : I didn't have any error message.

Thanks for your help.

Hi,

I currently have a CYBLE-214015-01 module which I plan to program, and I just bought a CY8CKIT-042-BLE-A.

May I know if I am able to use the baseboard as a debug tool to debug my CYBLE-214015-01 module?
If so, how? Can I just connect the SWD pins of the baseboard to the CYBLE-214015-01 module?

Also, are the codes transferable from the CY8CKIT-042-BLE-A to the CYBLE-214015-01 module?

Hello

I had tried HSSP using cy8c014LQI-422.

I'm stuck in DeviceAcquire() function.

I had compared my firmware waveform and cy3295 ttbridge waveform.

my firmware wave form shape is same but toggle frequency is 3 times slower than waveform of cy3295 ttbridge kit generate. 

Is there waveform timing diagram for HSSP?

I attached my project file.

Best Regards,

Sunghun noh

Hello

I have a design that uses the 4200M device (CY8C4246azi-M445).  I would like to add BLE support to this design.  Can you recommend a compatible device preferably one packaged into an FCC module with built in antenna?  I don't need all of the GPIOs that the CY8C4246azi-M445 has because I'm removing an LCD that will not be needed once BLE support is added.

thanks

Shawn 

Dear Sirs and Madams,

We are considering a PSoC4S UART (SCB) component. 

Therefore, we are verifying the problem due to the timing of UART communication.

The configuration of PSoC4S UART is as follows:

One frame of UART communication is as follows:

(1)

As in Expansion 1, the clock accuracy of PSoC 4S is +/- 2%.

Since one UART clock can have an error of 2%, there is a possibility that an error of 20% will occur in the final stop bit of 2% x 10 bits in 10 bits of one frame.

Is this perception correct?

(2)

As in Expansion 2, shows the relationship between RS-232C and PSoC4S master clock.

When the maximum error as in (1) is considered,

Do you know what number of the master clock the timing that PSoC4S takes the UART data into the register corresponds to?

Regards,

Hi,

I'm trying to use the PSOC Sensei's FIFOin component in polled mode on a PSOC 4 4200M CPU.

According to the datasheet, I should be able to enable the FIFO, check the status byte to see if it is not empty, and then read the head of the FIFO using the calls FIFOIn_1_Start(), FIFOIn_1_ReadStatus (), and FIFOIn_1_Read () respectively.

I call Start, I call ReadStatus in a tight loop until bit 1 (0x02) is set indicating the FIFO is not empty, but then when I  call Read, my program hangs.

Any ideas why calling FIFOIn_1_Read () would cause the micro to hang? Is the PSOC Sensei FIFOin component incompatible with PSOC 4? If so, is there any way to fix it?

I attached an archive of my workspace / project. It needs the FIFOin from this post added in as a dependency to compile.

https://community.cypress.com/t5/PSoC-5-3-1-MCU/Difficulties-using-the-parallel-input-bus-PI-in-UDBs/m-p/239226

I've never used a Cypress PSOC before so I'm trying the simplest possible way to pass data from my Verilog component to my software. The Verilog component just writes 'dead' to the FIFO at 4.096kHz then I'm trying to poll the status and fifo data registers to read them.

Thanks,
Glen