PSoC™ 4 Forum Discussions
Hi Community, Simple Question :
I have a .cyacd file and currently looking at Bootloader Host code to understand how it takes all the data into the Packets and transmit it one by one. I opened the .cyacd file in Notepad++ and saw Hex values. But the cyacd format contains the ASCII ?
Show LessHello
I added the "ble upgradeable stack" to my application. I trigger the OTA event using a characteristic. Everything works fine!
I do have one issue though. When I connect, disconnect and then perform a power on reset, the bootloader is triggered and "ota bootloader" is advertised. This happens even when I don't want to perform an application update. As per the application note, I've placed these two lines of code in main().
#if !defined(__ARMCC_VERSION)
InitializeBootloaderSRAM();
#endif
AfterImageUpdate();
I cannot share the complete code as it is proprietary. Anyway, I feel one of these lines is causing the issue to occur. Any advice is appreciated and let me know if you need more info.
Show LessHey, seems to be a problem with the Glitch Filter component, when interference with the same time width of the glitch is inserted into the glitch component, the output signal will be much longer than the insert pulse.
For example: if the GlitchFilter is supposed to filter pulses under 10[microsec], pulse of 9 micro will be filtered as expected, pulse of 11 micro will be outputed as expected, but pulse of around ~10 micro will be outputed around 126 micro.
What should I do?
Thanks
Show LessHello,
I try to program PSoC4 through cyflash and serial interface.
I downloaded and installed the Python version of cyflash from GITHUB.
The cyflash outputs on the screen that sends the following 7 bytes:
0x01, 0x38, 0x00, 0x00, 0xc7, 0xff, 0x17
But on logic analyzer and PSoC bootloader the following bytes are received (6 bytes):
0x7F, 0xEC, 0xFF, 0x71, 0x00, 0x74
Can you please advise what is the problem?
Thanks in advance.
Yacob.
Show Less
Hello,
I have CYBLE-012011 evaluation board and the project I am working on has a bootloadable component in it. The bootloadable points to the bootloader which is configured as a UART bootloader. When I compile and build the project, it generates .cyacd file. So far so good.
CYACD FILE
1. The first line contains 12 characters and the lines following has 269 characters each excluding the LF('\n') character.
But what I don't understand is in some cyacd files, the line ends with \r\n(CRLF) and in some cyacd files the lines end with \n(LF). Why is that?
I have attached a zip file(cyacd.zip) which has 2 cyacd files.
1. Blink,cyacd file is without the BLE component and each line ends with \n
2. firmwareImage.cyacd is with BLE component and each line ends with \r\n.
Suppose my flash data is :000000000.......789\r\n. What is being sent to the bootloader when bootloading using an embedded host using UART? Is CR part of the data to be sent?
Thanks
Dheeraj
Hi infineon
Q1)
Can CY8C4045AZI-S413 enter into sleep mode when using an external clock(48MHz) instead of an internal clock?
If so, are APIs and procedures the same for entering sleep mode with the internal clock and external clock?
Even with an external clock(48MHz), can device enter sleep mode just by executing only CySysPmSleep() API?
Or does user need to do some other processing if user use an external clock?
Q2)
Do you have data on current consumption(typ and max) in sleep mode when the external clock is 48MHz?
The data sheet has data on current consumption for 6MHz and 12MHz, but there is no data on current consumption(typ and max) when the external clock is 48MHz.
Q3)
Do you have any sample code that CY8C4045AZI-S413 enters into sleep mode?(external clock is 48MHz)
Best Regards.
YuMa
Show LessHi, Community,
Let me asked a question about how to set up the UART advanced tab.
I want to set the depth of the FIFO.
In this case, instead of putting a value in Tx Buffer, should I enter a variable in FIFO levels with Interruput enabled and the interrupt source selected as Tx FIFO level?
Best Regards,
Show Less