PSoC™ 4 Forum Discussions
Hi,
My code was written on PC #1, a Intel-base Win11 system. I copied the code to PC#2, a virtual machine (Vmware fusion) running Windows 11 ARM Edition on MacBook M3.
Both PC#1 and PC#2 have PSOC Creator 4.4. When I do Project -> Update Components, the Component Update Tool shows incorrect version numbers on PC#2, while PC#1 shows the correct versions.
On PC#2 (ie, Win11 ARM):
A similar error was reported here: https://community.infineon.com/t5/PSoC-Creator-Designer/Unable-to-update-components/td-p/360176
Since PC#1 is getting the right versions, I suppose PSoC Creator Update Server is up and running.
I suspect that PSOC Creator 4.4 was built with the Intel version of the C++ library so the creator is not compatible with the Arm64 version. Can anyone confirm?
Additional info:
PC#1 has Microsoft Visual C++ 2015-2022 Redistributable (x64) - 14.32.31326 and Microsoft Visual C++ 2015-2022 Redistributable (x86) - 14.32.31326
PC#2 has Microsoft Visual C++ 2022 Redistributable (Arm64) - 14.30.30704
Thanks!!
--Tony
Show Less
Although it is easy to call the internal __builtin_clz(x) from C to count leading zeros, how can this internal function be called from assembly? Thanks.
Show LessHi, Community,
I am trying to do an I2C communication project with CY8CKIT-041S-MAX.
I have almost finished writing the code, but when I build, I get an error about Cy_SCB_I2C_Enable (cy_scb_i2c.h).
I found a similar phenomenon in PSoC6 post.
To solve this problem, I tried to add the necessary files in the library manager, but that did not solve the problem.
If you know the best way to deal with this error, please let me know.
The error message is as below:
C:/xxx/build/APP_CY8CKIT-041S-MAX/Debug/main.o: in function `Cy_SCB_I2C_Enable':
make: *** [../mtb_shared/core-make/release-v3.2.2/make/core/main.mk:374: secondstage_build] Error 2
make[1]: *** [../mtb_shared/core-make/release-v3.2.2/make/core/build.mk:422: C:/xxx/build/APP_CY8CKIT-041S-MAX/Debug/mtb-example-psoc4-empty-app.elf] Error 1
undefined reference to `sI2C_InterruptHandler'
Best Regards,
Although the project build automatically saves the C files, it does not save any edited assembly files. Is there a way to force these files to save before building the project?
Show LessI am using Psoc Creator with cy8ckit-42 with a lengthy assembly file added to the simple blinky project. While the code has been building and running successfully and as it has gotten larger, adding an additional instance of a macro running correctly in other parts of the code causes the M0120 build error:
Build error: invalid offset, value too big (0x00000404)
The macro only accesses registers but has the instruction "ldr r1,=0x00010000" The disassembly shows the constant is accessed with a pc offset in another instance so I guess it must be this offset that is too large. Is the only way to deal with this is to declare the constant in memory? Thanks very much.
Show LessI have a product that uses a PSOC 4200 BLE. Customers complain that every couple of weeks or so, the BLE stops advertising. So it's a bug that pops up rarely. But it's pretty bad when it does! CyBle_SoftReset(); is not enough to bring the bluetooth back to life.
I don't know what it causing the bug, but I suspect the deep sleep transition. I am finding conflicting ideas regarding the allowable BLESS state for CPU Deep Sleep.
Here's the relevant part of my code:
blePower = CyBle_GetBleSsState();
if(blePower == CYBLE_BLESS_STATE_DEEPSLEEP || blePower == CYBLE_BLESS_STATE_ECO_ON)
{
st = SYS_ST_WAKE_FROM_DEEPSLEEP;
/* C11. Put system into Deep-Sleep mode*/
CySysPmDeepSleep();
}
In the auto-generated CyBle_Stack.h, I see that it is OK to put CPU to deep sleep with the CYBLE_BLESS_STATE_ECO_ON state:
/******************************************************************************
* Function Name: CyBle_GetBleSsState
***************************************************************************//...
* <td>CYBLE_BLESS_STATE_ECO_ON</td>
* <td>BLE Sub System is in process of wakeup from Deep Sleep Mode and ECO(XTAL) is turned on.
* CPU can be put in Deep Sleep Mode.</td>
* </tr>
...
* <td>CYBLE_BLESS_STATE_DEEPSLEEP</td>
* <td>BLE Sub System is in Deep Sleep Mode. CPU can be put in Deep Sleep Mode.</td>
* </tr>
...
CYBLE_BLESS_STATE_T CyBle_GetBleSsState(void);
However, I see here: https://github.com/cypress-speedycat/EasySleep/blob/master/source/EasySleep.c
that there is some controversy about using CYBLE_BLESS_STATE_ECO_ON as a valid state before entering deep sleep mode:
// NOTE: CyBle_GetBleSsState says CPU can be put to DeepSleep upon
// ECO_ON too, but that does not make sense since BLE is waking
// up then
Could an expert chime in on this? Is there a mistake in the CyBle_Stack.h file?
Hi Infineon.
Does PSoC 4100S Max(CY8C4148AZQ-S558) have the functions of “Software Transmit UART” of below link?
The link states the following, but how can I determine whether each device has “Software Transmit UART” functionality from datasheet or other documents of each device?
PSoC4 datasheet does not mention “Software Transmit UART” at all.
==================================================
The SW_Tx_UART supports PSoC 3, PSoC 4, and PSoC 5LP.
==================================================
Best Regards.
YuMa
Show LessI'm working with the CYBLE Pioneer Kit. I'm trying to switch between two different connection intervals. The purpose is to change modes, between high throughput and low power modes.
Mode 1 is fast and responsive, at the expense of battery power.
Mode 2 is the low power mode. It is too slow for user-interface activity, but it's just enough to keep the connection alive.
In the final product, the device will idle in Mode 2 for low power. When the user pushes a button, it will switch to Mode 1 for a while, and then revert to low power mode after a timeout.
To test this, I modified the code example Day019_Connection_Parameters, so there are two sets of connection parameters:
CYBLE_GAP_CONN_UPDATE_PARAM_T connectionParameters_1 =
{
12, /* Minimum connection interval - 12 x 1.25 = 15 ms */
24, /* Maximum connection interval - 24 x 1.25 = 30 ms */
0, /* Slave latency - 1 */
500 /* Supervision timeout - 500 x 10 = 5000 ms */
};
CYBLE_GAP_CONN_UPDATE_PARAM_T connectionParameters_2 =
{
160, /* Minimum connection interval - 160 x 1.25 = 200 ms */
160, /* Maximum connection interval - 160 x 1.25 = 200 ms */
29, /* Slave latency - 1 */
1800 /* Supervision timeout - 1800 x 10 = 18000 ms */
};
To toggle between them, I just test one of the LEDs that toggle when the user button on the Pioneer Kit is pushed:
if (Led_Green_Read() == 1)
CyBle_L2capLeConnectionParamUpdateRequest(cyBle_connHandle.bdHandle, &connectionParameters_1);
else
CyBle_L2capLeConnectionParamUpdateRequest(cyBle_connHandle.bdHandle, &connectionParameters_2);
The behaviour is almost exactly as expected, toggling between the two modes whenever the user button is pressed. When the device is in Mode 1 (fast mode) and the button is pressed, Mode 2 activates within a few seconds.
However, to go back to Mode 1, there is a very long lag time (between 30-60 seconds). This is what I would like to understand.
The peripheral (the CYBLE) is acting quickly. However, the central (CySmart) is very slow to respond. This is shown by the two BLE stack events:
- CYBLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP shows that CySmart receives and accepts the request very quickly in each case. Then (I presume) CySmart must process the request and modify the central's BLE connection settings. When this is complete, it announces the next stack event, which (eventually) arrives at the peripheral as:
- CYBLE_EVT_GAPC_CONNECTION_UPDATE_COMPLETE.
The long delay occurs between these two stack events. In Windows CySmart, this delay varies between 45-60 seconds. Android CySmart is a little better, at about 30 seconds.
Questions:
- Is this delay something peculiar to CySmart, or is this expected from all BLE devices and apps?
- Why does it vary across BLE platforms (Android, iOS, Windows)?
- Is there a programming trick that would allow the central device to process the Connection Parameter Update Request more quickly?
Thanks for your collective knowledge.
Show Less
Getting errors when trying to build project with components cy_isr_v1_71, cy_boot_v6_10, and LIN_Dynamic_v6.
This seems to be a similar issue to other forum posts, I've tried uninstalling and reinstalling PSOC Creator 4 with no luck.
Show Less
Hi Infineon.
Does PSoC4/6 have data flash like the below link?
If there are PSoC4 and PSoC6 devices with data flash, could you please let us know their series names?
https://www.renesas.com/jp/ja/document/dst/rx610-group-datasheet-rev120?language=en&r=1054406
Data flash is a different flash than usual flash, and is used to store data that is frequently rewritten.
Therefore, rewrite/erase cycle of data flash is higher than usual flash.
In above link, rewrite/erase cycle of usual flash is 1000 times, but rewrite/erase cycle of data flash is 30000 times.
Please confirm P79 and P80 of link document.
- (P79) 5.6 ROM (Flash Memory for Code Storage) Characteristics
- (P80) 5.7 Data Flash (Flash Memory for Data Storage) Characteristics
Best Regards.
YuMa
Show Less