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PSoC 4

RoJa_1564316
New Contributor

Hello,

I'm getting error "Warning-1350: Asynchronous path(s) exist from "Clock_1" to "\Timer_1:cy_m0s8_tcpwm_1\/tr_overflow"".

I have reduced components for this problem to the following design

RaceProblem.png

If I exchange the NOT component with Sync component, there is no error any more. But datasheet remarks:

s_in – Input

Signal to be resynchronized. The signal must have a pulse width of at least one clock period plus 2 ns.

I think, ov will only be high for one cycle of Clock_1. So, is this solution ok or is there any other solution ?

Regards Rolf

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1 Solution
Ekta
Moderator
Moderator

Hello Rolf,

Using a SYNC component instead of NOT should work fine.

You can refer to the document 'Digital Design Best Practices' , page 24: https://www.cypress.com/file/179061/download .

In figure 34, the input to the sync component is 'tc' which is also high for one clock cycle.

pastedImage_7.png

Best Regards

Ekta

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2 Replies
odissey1
Honored Contributor II

r.s.jahn,

Options:

(1) Set input pin DCC_unfiltered input to "Syncronized".

(2) Leave Sync in place of NOT, but use BUS_CLK clock (MASTER_CLK on PSoc4?)

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Ekta
Moderator
Moderator

Hello Rolf,

Using a SYNC component instead of NOT should work fine.

You can refer to the document 'Digital Design Best Practices' , page 24: https://www.cypress.com/file/179061/download .

In figure 34, the input to the sync component is 'tc' which is also high for one clock cycle.

pastedImage_7.png

Best Regards

Ekta

View solution in original post

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