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AlTe_4253701
Level 2
Level 2

I am using SPI 8 bits Iand I see some wrong values in the scope

First Byte : 0

Second Byte: 0

Third Byte : 0x81

Why in first and second byte I have an error as you can see in SCR02 , this represent MOSI and CLK

SCO1 CS and CLOCK

Regards

Albert

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3 Replies
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi AlTe_1513551​,

The scope shots look fine. Can you please elaborate your issue with a project?

Regards,

Bragadeesh

Regards,
Bragadeesh
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RX Interrupt only. and we use Slave Select STALL

Both SPI are shared by Multiplexer and De multiplexer . in order to share same pins 8 Bit  Speed 700 KHz

if (cs ==2) {

       Select_SPI(MULTI_AD9520);                                     // Select MuxDemux 0 for 16 bits operations 

        CyDelayUs(5);

   

    }else {

        Select_SPI(MULTI_AD9910);

      }

   

                    buffer_length =0;                                                                           // reset pointer

    Indx_rd =0;                           // Clear RD Buffer

    Indx_wr  =0;                          // Clear WR Buffer

  

   

         /* RX SPI2 Only */

          SPIM_2_RX_STATUS_MASK_REG = ((uint8) SPIM_2_STS_RX_FIFO_NOT_EMPTY );

         

    /* Clear Hardware RX FIFO */

    while(0u !=(SPIM_2_RX_STATUS_REG & SPIM_2_STS_RX_FIFO_NOT_EMPTY))

    {

        (void) CY_GET_REG8(SPIM_2_RXDATA_PTR);

    }

   

   

    // First byte     

    SPI_Buffer_wr[buffer_length++]= (buffer[Indx++]);// &0xFF00)>>8);

   // SPIM_2_RX_STATUS_MASK_REG = ((uint8) SPIM_2_STS_RX_FIFO_NOT_EMPTY );

    CY_SET_REG8(SPIM_2_TXDATA_PTR, (unsigned char )SPI_Buffer_wr[Indx_wr++]);

    while(!(SPIM_2_ReadTxStatus() & SPIM_2_STS_SPI_DONE)); //Wait for transaction to complete.

    CyDelayUs(AD9520_INTERBYTE_DELAY);                     //delay xxx micro second

  

                                                                 

  

   

    //Second byte

    //Control_Reg_1_Write(Cntrl_Register_1 =Cntrl_Register_1 & ~CNTR_REG1_SS2);

    //Indx_rd=0;

    //Indx_wr=0;

  //           SPIM_2_TX_STATUS_MASK_REG  = ((uint8) (SPIM_2_STS_SPI_DONE ));

    SPI_Buffer_wr[buffer_length++]=buffer[Indx++];// (temp & 0x00FF);

  //  SPIM_2_RX_STATUS_MASK_REG = ((uint8) SPIM_2_STS_RX_FIFO_NOT_EMPTY );

    CY_SET_REG8(SPIM_2_TXDATA_PTR, (unsigned char )SPI_Buffer_wr[Indx_wr++]);

    while(!(SPIM_2_ReadTxStatus() & SPIM_2_STS_SPI_DONE)); //Wait for transaction to complete.

    CyDelayUs(AD9520_INTERBYTE_DELAY);                     //delay xxx micro second

  

      do{

          SPI_Buffer_wr[buffer_length++]=buffer[Indx++];                                                       // Compatibility   with TX INT handle

    //      SPIM_2_RX_STATUS_MASK_REG = ((uint8) SPIM_2_STS_RX_FIFO_NOT_EMPTY );

          CY_SET_REG8(SPIM_2_TXDATA_PTR, (unsigned char )SPI_Buffer_wr[Indx_wr++]);

          while(!(SPIM_2_ReadTxStatus() & SPIM_2_STS_SPI_DONE));                //Wait for transaction to complete.

          CyDelayUs(AD9520_INTERBYTE_DELAY);                                    //delay xxx micro second

        

       

       

    }while (Indx != *array_lenght);

         //Total reading 3 bytes/ 

      while(Indx_wr != Indx_rd);      

Regards ALbert

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Could you please share the PSoC Creator project file focusing on the issue? Please refer to the following link to send us the zipped version of the project

Archiving a PSoC Creator Design

Regards,

Bragadeesh

Regards,
Bragadeesh
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