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PSoC 4

Anonymous
Not applicable

Page 94 of the TRM (section15.2.2 and figure 15-1 specifically) shows that the SCB MISO line is tri-stated when the SCB is not selected by the SPI master. This is excellent news for me, but I don't see anywhere in that section where it is explicitly stated that the SCB tri-states the MISO line when the SCB is not selected.

   

 

   

Has anyone used the SCB where tri-stating the MISO line was a requirement in the design? I see a reference to SID172 and Thso in the AC characteristics but no timing diagram to give me the warm fuzzy feeling that these AC characteristics refer to what I think they refer to (how long it takes the SPI slave peripheral to tri-state MISO when the device is no longer selected).

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Anonymous
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 Answering my own question -- "Enable Multi-Slave mode" in the advanced tab is what does it.

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Anonymous
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 Nope, un-answering my own question.

   

 

   

In UDB mode (i.e. for PSoC4 and 5LP), there is a "multi-master" mode which brings an OE signal out. My question was for the SCB SPI slave mode. Is there a definitive answer in the Cypress documentation or from someone here that states whether the SCB SPI slave MISO pin is tri-stated when the SCB SPI slave is not selected?

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Anonymous
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I got the same problem.

   

In SCB mode, the MISO pin appear to never goes in high-impedance. A simple solution is to put an external tri-state buffer.

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Anonymous
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Sorry, my bad...

   

The PSoC4 Cy8C4245AXI put the pin MISO in high impedance if the SS is not asserted. Work perfectly!

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