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PSoC 4

Mrinal
New Contributor II

I am using two PWM modules both driven by the same clock.

   

PWM1 period = 99

   

PWM2 period = 9

   

Therefore in each cycle of PWM1, there are 10 cycles of PWM2. Everything works just perfect till here and the oscilloscope shows perfectly alligned outputs as expected.

   

Now, when I prescale PWM1 by 2x in the initial property window, PWM2 should complete 20 cycles in each one cycle of PWM1. It indeed does, BUT there is a phase shift of one clock period between PWM1 and PWM2. It doesn't end here. Instead of setting the prescaler to 2x in the initialization window, if I use the SetPrescaler() function in the code, the phase shift disappears!

   

In short, the PWM module works differently depending upon whether the Prescaler value has been set in the components initialization window  or whether it is set through programming.

   

Why is this happening?

   

Thank you...

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3 Replies
Bob_Marlowe
Expert II

Can it be that the point relative to the clock when the prescaler is started is causing the phase shift? There is a point where it starts and when that is on the second clock cycle you will see a phase shift.

   

 

   

Bob

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Bob_Marlowe
Expert II

Can it be that the point relative to the clock when the prescaler is started is causing the phase shift? There is a point where it starts and when that is on the second clock cycle you will see a phase shift.

   

 

   

Bob

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Mrinal
New Contributor II

I think the prescaler starts on the first tick of the clock and begins counting from the  next tick after starting, therefore it misses one complete clock cycle and results in a phase shift of one clock.

   

I used two flip flops back to back in a shift register configuration to delay the leading PWM signal by one clock period. It works just fine and the two PWM outputs are perfectly alligned.

   

But the problem is that the common clock to the PWM and Flip Flops cannot exceed 12MHz which is half the HFCLK frequency. Beyond 12MHz this clock cannot be used to drive UDB components 😞

   

Is there a way to route fast clocks to the UDB?

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