PSOC 4 BLE Set WDT interrupt priority

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manusharian
Level 4
Level 4
25 replies posted 10 replies posted 10 questions asked

Hello,

   

I basically want to achieve the following behavior using WDT0 timer but in this moment I face 2 problems.

   

Use case: Start the WDT0 for about 10 ms (327 for match value); When expire, set a pin on 1 and start the WDT for about 0.28 ms ( 9 in match value). When this expire start ADC conversion, wait for result, start WTD0 for about 0.04ms (1 in match value). When this last time expires set the pin on 0. So basically at each 10 ms I want to create a signal on 1 for about 0.32 ms, like a clock but I want it to run also in deep sleep mode.

   

First problem is when set a match value < than 5 the CPU resets itself. I do not know why but with 5 in match value it is working but obvious the time is more than the 0.04ms wanted.

   

Second problem is caused by the interrupt priority as I expect because when run whitout any other component the 0.28 ms time is ~0.24ms and the adc conversion takes 10 uS as expected. On the other hand, when I run my application which includes other components like I2C, BLE, ADC, WDT1, etc; the time is about 0.89 ms (instead of 0.32 ms). I expect that the interrupts from I2C, BLE and others comes in and therefore delays the interrupt for WDT0. I do not need exact times, but close. So it is ok to have lets say 20-30 us delays but not 3 times the expected time.

   

Therefore my questions are: how to set the WDT0 interrupt to the highest priority to make my pulse? And, of course, why I cannot set a value les than 5 on math register?

   

Other details: Before  start first the WDT0 I set this:

   

/* Setup WDT Counter 0 to generate interrupt on match */
    CySysWdtWriteMode(CY_SYS_WDT_COUNTER0,CY_SYS_WDT_MODE_INT);
    /* associate a callback to wdt interrupt */
    CySysWdtSetInterruptCallback(CY_SYS_WDT_COUNTER0, WDTCompareMatchCallback);

   

Then When I start the WDT I do :

   

 /* Write match count */
    CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0, XXX); // XXX 327, 9, 1
    /* Enable clear of counter on match */
    CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, 1u);
     /* Enable WDT counter 0 */
    CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK); 

   

Every time I reload a match value I do

   

/* Stop timer */
    CySysWdtDisable(CY_SYS_WDT_COUNTER0_MASK);

   

 

   

Thank you!

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1 Solution
Anonymous
Not applicable

Hi Marian,

   

As you know, WDT is clocked by LFCLK. Is the LFCLK set to ILO or WCO in your design? WCO is more accurate. If you had set it to ILO, then there can be variations in actual WDT period.

   

Ideally, BLESS should be given the highest priority. You can set the interrupt priority under: interrupts tabs in .cydwr.

View solution in original post

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9 Replies
Anonymous
Not applicable

Hi Marian,

   

As you know, WDT is clocked by LFCLK. Is the LFCLK set to ILO or WCO in your design? WCO is more accurate. If you had set it to ILO, then there can be variations in actual WDT period.

   

Ideally, BLESS should be given the highest priority. You can set the interrupt priority under: interrupts tabs in .cydwr.

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Hello,

   

The WDT is set to WCO and the ILO is completely stop in my design. In the interrupt tab I only got I2C, BLESS and ADC and they are set on default. I think this is because I set the interrupt in SW and attached a callback there. Also besides this I also have WDT1 set as a timer(for code blocking) and for scheduler.

   

I will make more test about this!

   

Thanks.

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Anonymous
Not applicable

I'm not undetstanding why you would use the WDT instead of the TCPWM module, as it will function during sleep (afaik). 

   

Relating to using the WDT specifically, I believe there was mention somewhere in the documentation that the WDT will interrupt pre-emptively in some instances (not sure where though 😕 ).

   

I believe that is why you have a minimum match value of 5 as well.

   

The TCPWM is intended to be used for PWM clocking (as your case sounds like), and the WDT is inteded to be used for preventing the chip getting locked-up if an error or incorrect case occurs.

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Hello,

   

The PWM will not work because the PWM is not working during deep sleep as I know. The application I am working with is intended to be a wearable where the power consumption is of high interest therefore we put the device in deep sleep as often as possible.

   

Thanks for pointing out the interruption cases for WDT. I will definitely check more into that!

Anonymous
Not applicable

Ah, I was thinking it was Sleep mode. Looking at the software I'm using, I was also forced to use the WDT for a timer, but my application is for a remote-control, so it was being used as a "keep-alive" for tracking when the battery goes dead on the unit.

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

You are right.

   

But

   

The WDT can be used to manage a timer which runs during deep sleep. The TCPWM (and many other components that depend on a high frequency clock) will not run in deep sleep.

   

 

   

Bob

Hello Bob,

   

You are correct!

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Anonymous
Not applicable

can i have the source code for cypress-ble -beacon

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himam_31
Employee
Employee
50 likes received 25 likes received 10 likes received

Hello,

   

BLE Beacon tool is proprietary to Cypress. The source code of the tool if confidential and hence cannot be released. Is there any specific information regarding the tool which you would like to know?

   

Thanks,

   

Hima

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