Anonymous
Not applicable
Feb 16, 2018
09:43 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Feb 16, 2018
09:43 AM
I have a design where I am getting the warning:
Warning: sta.M0021: project_timing.html: Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "CyHFCLK". See the timing report for details.
This warning is not an error in my design, as I know that the data is stable for the time period that I am registering it. I'd like to have permanently ignore this warning, so it doesn't show up on every build.
Is there a timing constraints file (like those found in FPGA tools) or other method that I can have the tools ignore this path?
Brian
Solved! Go to Solution.
1 Solution
Feb 16, 2018
12:02 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Feb 16, 2018
12:02 PM
2 Replies
Feb 16, 2018
12:02 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Feb 16, 2018
12:02 PM
I would suggest to add a ClockSync component.
Bob
Feb 25, 2018
10:56 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Feb 25, 2018
10:56 PM
The following apps note may be helpful.
AN81623 - PSoC® 3, PSoC 4, and PSoC 5LP Digital Design Best Practices
Roy Liu