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PSoC™ 4

Anonymous
Not applicable

Hi,

   

This is my first study for PSoC device.

   

I need a function to emit variable frequency like DDS24 (It discussed on PSoC 5 forum), and I need BLE feature on same device. Thus, I select PSoC 4 BLE device for my case study, and I got a CY8CKIT-042-BLE Bluetooth® Low Energy (BLE) Pioneer Kit  to verify the features.

   

I only need a software control frequency to generate out1, fixed phase shift 180 for out2, and another hardware/software “enOut3” to control output for out3.( all of out1/2/3 with same frequency  ).

   

I load DDS24 library to my project, PSoC Creator 4 Update 1 builder shown the resource is not enough to fit on the device. Thus, I erase some feature of control register in DDS24_Core_v0_0.v, and use a fixed parameter for < tune_word > to get fixed frequency generation. Yes, It is workable, the resource meter shows “MacroCells 29/32, Unique P-terms 27/64, Datapath Cells 0/4, Status Cells 1/4, Control Cells 0/4”.

   

But, I need a API runtime controlled frequency entry for my project. My first question, if we can use DataPath elements, it may reduce the resource of Marcocells used, and we can get more resource to fit all features on the device. 2nd question, how can I to use a precision clock source for DDS24 ? It looks source comes from internal 48MHz to generate a lower clock source as 3MHz that I need, but, the error is too big to match my requirement, I wish to use the source comes from external crystal 24MHz, not internal 48MHz.   

   

Has it any chance to implement ? 

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1 Solution
odissey1
Honored Contributor II

yuhua,

   

sorry for late reply, I don't get notifications on this thread. Bringing "reset" pin HIGH will reset DDS32 accumulator to 0. To do this using SW call, attach a ControlReg of width 1, set it to PULSE mode, attach a BUS_CLK to it for sincronization and call API command to make a single cycle pulse:

   

ControlReg_1_Write(1);  

View solution in original post

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9 Replies
odissey1
Honored Contributor II

yuhua,

   

The DDS24 component was implemented entirely in PLD. It consumes about 75% of the UDB resouces on P4200 when only single output is enabled (no phase output). Unfortunately, the 6 remaining macrocells are not enough to implement quadratures.

   

The solution is not to use DDS24 component, but to use similar (but simpler) component DDS32. It has less features (no phase output), but it implemened entirely in UDB datapath, and in result, leaves plenty of macrocells avaialble for quadrature pair output generation. The project and DDS32 component are attached. I also noticed that on P4200 component has some issues: it runs OK in 24-bit mode, but not in 8-, 16- or 32-bit (no issues on PSoC5). Hope that 24-bit resolution is enough for your application. The DDS32 component datasheet is not available at this moment, so for general description please refer to DDS24 datasheet.

   

   

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odissey1
Honored Contributor II

yihua,

   

regarding you other question " I wish to use a 3.0 MHz clock source for DDS24, and it divided from external crystal 24.0 MHz on PSoC 4 BLE pioneer kit, Have I any chance to implement?".

   

-I can't draft an example for you, as I have no XTAL on my P4200 board (it is not BLE-enabled). Your question is not DDS32-related, but rather Pioneer-BLE kit related. I suggest to post separate question in PSoC4 BLE forum (e.g. "How to derive a 3MHz clock from XTAL on Pioneer BLE board?".  

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Anonymous
Not applicable

Odissey,

   

Sorry, bother you to reply this question. I got the solution for Clock already. Thanks. 

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Anonymous
Not applicable

Hi, Odissey,

   

Thank for your help! It is workable. I notice this implement with some different with DDS24 project, it added a new "reset" pin, I guessed " it will be reset accumulator to 0 if we need to change a new frequency.", DDS24 project was not support this function, thus, it will  generate waveform follow the last timing,  it will not restart a new one. Is my guess correct ?

   

How can I control the "Reset" by software control ?
Thanks a lot.

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Anonymous
Not applicable

When you are referring to controlling the "Reset" by software control, I assume you mean:

   

Setting the Pin high/low with software. Simply set the pin high or low using the cypress API functions for Pin control.

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Anonymous
Not applicable

Pratt,

   

You mean to use pin high or low ( \Cypress\Logic\Logic High '1'  or Logic Low '0' ), it is permanent setting. I have tried to set logic 1 / 0 that its behavior looks like to Disable / Enable the component in this example, I can not watch the behavior of "reset" is meet my requirement or not.  Because it can not be controlled dynamically.  

   

Thanks.

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odissey1
Honored Contributor II

yuhua,

   

sorry for late reply, I don't get notifications on this thread. Bringing "reset" pin HIGH will reset DDS32 accumulator to 0. To do this using SW call, attach a ControlReg of width 1, set it to PULSE mode, attach a BUS_CLK to it for sincronization and call API command to make a single cycle pulse:

   

ControlReg_1_Write(1);  

View solution in original post

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Anonymous
Not applicable

Odissey, 

   

Thanks for your reply, Please attach example files, I think that it is difficult to me for understanding and implement function. Or, please point it where can I find it.

   

 ControlReg_1_Write(1);  // --- It is not a general function.

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odissey1
Honored Contributor II

I attached project in the above post. Typically reset is not required. For example, changing frequency occures as soon as new value is set by SetFrequency(), reset is not required.

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