Hardware Detect to Buffer not possible?

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Anonymous
Not applicable

I am trying to use the 9-bit address mode with hardware address detection on a CY8C4245 and although it it one of the biggest PSoC 4 devices the design is not fitting (Resource limit: Maximum number of UDB Unique Pterms exceeded (max=64, needed=74)

   

Is there a way to get this functionallity in a PSoc 4 device? If not, why is it selectable in PSoC Designer? It's frustrating when advertised functions are not working in the real world...

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ETRO_SSN583
Level 9
Level 9
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It would help if you could post the project for the forum to

   

look at the entire resource demand and other issues like

   

code, etc..

   

 

   

    

   

          

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

 

   

 

   

Regards, Dana.

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HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

There was a similar discussion a while ago. Are you sing Half-duplex by any chance? The problem here might be again that the number of PTerms needed cannot be fit into the UDBs - the number of connections for that is then to big.

   

The UDB component is actually the same for all PSoC parts, thats why there are no special precautions for PSoC4 with limited resources. (btw: the upcoming 4200L series has 8 UDBs - see the roadmap)

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Anonymous
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I use Full Uart, 9 Bit, Mark/Space Parity (there seems to be another issue with that....) and Hardware TX Enable. There is nothing else in the Project.

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ETRO_SSN583
Level 9
Level 9
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Yes, per datasheet resources are exceeded -

   

 

   

   

 

   

Parts coming in Fall timeframe with 8 UDBs -

   

 

   

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Anonymous
Not applicable

If I disable the "Hardware detect to buffer" feature it fits in a CY8C4245, but if I switch to "Half Duplex", which should use less resources, the creation process fails (E2071: Unable to pack the design into 4 UDBs). It doesn't matter if "Hardware TX-Enable" is used or not.

   

Could it be that there is something wrong with the v2.40 UART component?

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ETRO_SSN583
Level 9
Level 9
100 sign-ins 5 likes given 1000 replies posted

Consider filing a CASE and posting back to forum answer -

   

 

   

    

   

          

   

To create a technical or issue case at Cypress -

   

 

   

www.cypress.com

   

“Support”

   

“Technical Support”

   

“Create a Case”

   

 

   

You have to be registered on Cypress web site first.

   

 

   

Regards, Dana.

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HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

The Half-Duplex version needs less UDB/Datapath resources, right.  But since it switches, during runtime, the functionality of them between send and receive, the logic it uses internally is more complicates. And for that a too large number of combinatorical terms is needed.

   

It seems Cypress needs to rework this implementation, so a Support case should be the next step. (The component is not defective as such on the PSoC4, the same problem can happen on a PSoC5 although there the larger number UDBs defers the problem somewhat)

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