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PSoC™ 4

GrLe_1336286
New Contributor II

Hi All,

Due to global chip shortages we are attempting to migrate a working PSoC project to an alternative device.

The migration is from a CY8C4245LQI-483 to a CY8C4244LQI-443.

It seems that a hard fault is triggered in the built-in interrupt handler when reading a register.

To debug we have built the project with only the SCB (I2C) component. When only the I2C component initialised the hard fault occurs, and does not happen when the device is not initialized.

Attached is a capture from debug showing the file and line that seems to cause the error, other interrupts may or may not happen before this interrupt, but on multiple power cycles the problem consistently occurs on this specific line in this specific ISR, before triggering the default handler.

SCB component version is 4.0.

Any thoughts on how we can approach this issue?

Regards,
Greg

 

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5 Replies
Ekta
Moderator
Moderator

Hello Greg,

Could you please let me know if you made any changes in your project which changing the MPN from CY8C4245LQI-483 to CY8C4244LQI-443? If yes could you please let me know what are the changes you made?

Could you please attach your project so that we can check the configuration and the code?

Also, can you try programming an already existing code I2C Slave example: https://www.cypress.com/documentation/code-examples/ce222306-psoc-4-i2c-communication-serial-comunic...
 and let us know if you face the same issue?

Make sure you change the device MPN and choose the correct pins for your device while testing the code example.

Best Regards
Ekta

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GrLe_1336286
New Contributor II

Hello Ekta,

Thank you for the reply.

When changing between the two PSoC devices significant changes were made. This is a result from changing from the larger device with 4 UDB compared to 2 UDB.

We have changed our project to use only the I2C communications block but the issue persists. Do you have a direct email to provide the archived project? This code is proprietary.

In addition, we note that when the PSoC programmer (MiniProg) is connected the PSoC does not fault between power cycles. With the MiniProg disconnected the unit always hard faults. We are looking into this additional behaviour.

Regards,
Greg

 

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GrLe_1336286
New Contributor II

Hi All,

Brief update.

We have rebuilt the project for the original device CY8C4245LQI-483. The same code which hard faults on the on the CY8C4244LQI-443 operates correctly, no hard fault is seen.

For the project compiled with the CY8C4244LQI-443, we have switched between Release and Debug builds, disabled small optimization and several other changes with the same issue. The hard fault behavior does change however it is not always consistent.

We are arranging for additional boards to have the CY8C4244LQI-443 fitted in place of the CY8C4245LQI-483 so we can provide a wider range of test data.

Regards,
Greg

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Ekta
Moderator
Moderator

Hi @GrLe_1336286 

We tested the project you had sent on the CY8CKIT-042 which has the CY8C4245AXI-483 device and when debugging the project it never went to hard fault.

Since you have mentioned earlier that "we note that when the PSoC programmer (MiniProg) is connected the PSoC does not fault between power cycles. With the MiniProg disconnected the unit always hard faults. We are looking into this additional behavior" I think this might also be related to the power. Can you try measuring the power on the Vccd and Vddd pins when using the CY8C4244LQI-483 device which causes the hard fault.

Since the issue does not occur on the CY8C4245LQI-483 (original device) could you let me know if you are testing the project with the older device and newer device using the same board? or are you using different boards for each device?

Best Regards
Ekta

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GrLe_1336286
New Contributor II

Hello Ekta,

Thank you for your help in pursing this issue.

We have tested two additional CY8C4244LQI-483 devices from the same batch (date code) without any issues. The DC 5 V power rails appear fine, supplied from a 3A switch mode, so we will change this PSoC device to a newer batch to confirm operation of the board.

Kind regards,
Greg

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