ARM Cortex M0 VTOR register

[masu_1341616]

Hello,

Cortex M0 + can be set in ROM by the VTOR register.

Normally, it is set in RAM as follows by initialize_psoc () of Cm0plusStart.c.

CYREG_CM0P_VTOR = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM

The above process is set to ROM (address: 0x0), which is the initial value of Cortex M0 +, without this process.

In this case, the vector table is allocated to ROM, but is there any particular effect on the interrupts used by CapSense or EZI2C?

Thanks

[AikoO_51 · Accepted solution]

Current CapSense/EZI2C interrupt features are implemented on RAM Vector table bases (VTOR = 0x20000000 (RAM)).

The interrupt handlers for CapSense/EZI2C are mapped to each IRQ in vector table in RAM.

(please check CapSense_ISR_SetVector() function in CapSense_ISR.c)

If “CYREG_CM0P_VTOR = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM” is commented out, Vector table still is located in ROM.

When CapSense interrupt happens, IRQ16 in vector table in ROM will be proceeded. However, the interrupt handlers for CapSense is NOT mapped to IRQ16 in vector table in ROM. So, its interrupt will not be handled correctly.