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we are trying to re flash the Micro Via MODUS tool .it is getting heat while flashing after 60% completed. and our tool shows power interrupt .
Error Image from our flashing tool:
please support to resolve this issue. we are struggling to Re flash the Micro . kindly share your input to resolve the issue.
Show LessHello,
I am trying to understand the working of various peripherals for the TC397 board. I came across the IfxPort_reg.h file for GPIOs and noticed that there are some missing nos. in the port modules for example after MODULE_P00, MODULE_P01, and MODULE_P02, there is no MODULE_P03. It skips directly to MODULE_P10. More examples can be seen in the screenshot below. I am not sure if this is common knowledge, but is there any particular reason the port modules are named in such a way?
Thanks
Show Less
Hi,
I am using CY8C6245LQI-S3D42 and I used the DFU examples to boot the system and created the application to run on AM4 core and everything is working well.
I wait for 5 sec in DFU to check if there is any updates or just move with the Application code.
I find that sometimes the device stops booting once in a blue moon. Now If I flash again just the boot loader, everything is fine , I need not have to write the Application, it moves from DFU in 5 sec to application.
I believe, there is some how the flash/DFU is getting corrupted. I want to protect this scenario. Can some one share how do I protect my DFU so that it never erases . Any example's will be appreciable, I am using USB CDC transport in DFU.
Regards,
Madhav
Show LessHi Team,
Do we have System Tick timers for S6J3370 Controllers
Dear All,
I use the DAVE ide v4 with the nano library, calling the SPI-MASTER-EnableSlaveSelectSignal() and SPI-MASTER-DisableSlaveSelectSignal() functions cannot raise or lower the CS pin of SPI. However, when sending data through SPI, when using an oscilloscope to check the status of SCL and MOSI pins, they generate waveforms that are normal, but the CS pin remains in a high level state.
Configure this CS pin as an IO port, manually pull up or down the CS pin, but use the BUSY flag in the TBUF register as the completion of sending. When pulling up the CS pin, there will be a situation where there is still one byte that has not been sent, but the CS pin has been pulled up.
What may be the reason why the two API functions generated by calling cannot control the CS pin state; How can I avoid manually raising or lowering the CS pin when there is still one byte of data not sent?
Thanks.
Show LessHello,
I'm running MTB 3.2 GUI in Ubuntu 22.04.4 LTS and building the Security_App PSoC6 example for the Prototyping Kit (CY8CPROTO-062-4343W).
After creating the default Security_App example, I added the emeeprom (v2.20.0) component, so as to read/write settings to the PSoC6 32kB Auxilliary Flash. I copied the code from Emeeprom's README.md
And added a line CY_SECTION(".cy_em_eeprom") , so that emEepromStorage will be kept in the 32kB Auxilliary Flash.
However, the code failed to compile:
/opt/Tools/ModusToolbox/tools_3.2/cymcuelftool-1.0/bin/cymcuelftool --merge ../proj_cm0p/build/APP_CY8CPROTO-062-4343W/Debug/proj_cm0p.elf ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/proj_cm4.elf --output ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.elf --hex ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex; cp -f ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app_BOOT_raw.hex; rm -f ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex; /opt/Tools/ModusToolbox/tools_3.2/gcc/bin/arm-none-eabi-objcopy --change-addresses=0 -O ihex ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.elf ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app_BOOT_unsigned.hex; ../../mtb_shared/core-make/release-v3.3.1/make/scripts/python3.bash ../../mtb_shared/mcuboot/v1.8.1-cypress/scripts/imgtool.py sign --header-size 0x400 --pad-header --align 8 -v 1.0.0 -S 917504 -M 1792 --overwrite-only -R 0 -k ../proj_btldr_cm0p/keys/cypress-test-ec-p256.pem ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app_BOOT_unsigned.hex ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex; cp -f ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex ./build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app_BOOT.hex;
No ELF section .cychecksum found, creating one
Application checksum calculated and stored in ELF section .cychecksum
No ELF section .cymeta found, creating one
Checksum calculated and stored in ELF section .cymeta
Usage: imgtool.py sign [OPTIONS] INFILE OUTFILE
Try 'imgtool.py sign -h' for help.
Error: Image size (0x3fe0896) + trailer (0x20) exceeds requested size 0xe0000
make[1]: Leaving directory '/home/ub2204/work/psoc/tansiowk_mtw_3_1/Security_App_Emeeprom/proj_cm4'
cp: cannot stat './build/BOOT/APP_CY8CPROTO-062-4343W/Debug/primary_app.hex': No such file or directory
make[2]: *** [../../mtb_shared/core-make/release-v3.3.1/make/core/bwc.mk:161: _mtb_build__legacy_project_postbuild] Error 1
make[1]: *** [../../mtb_shared/core-make/release-v3.3.1/make/core/main.mk:385: secondstage_build] Error 2
make: *** [/opt/Tools/ModusToolbox/tools_3.2/make/application.mk:72: build] Error 2
"/opt/Tools/ModusToolbox/tools_3.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=/opt/Tools/ModusToolbox/tools_3.2 CY_IDE_BT_TOOLS_DIR= -j6 all" terminated with exit code 2. Build might be incomplete.
I have attached the code, build error log and map file.
Thanks for any advice!
BR,
SK
Show LessHi,
i would like to connect an external nor flash memory from ISSI to the XMC7100 EVK board (preferably through qspi or through spi). How can i do this? which gpio pins are available and how can I configure this in through the Eclipse IDE for ModusToolbox.
I would ultimately want to connect the serial flash write/read application.
Best regards,
PrasadA
Show Less你好!
在NORMAL状态下,我用WriteRow写NAR时报0xF00000AA(Writes are disabled in safety register)错误,
请问是什么原因?另外,可否提供使用WriteRow的例程?谢谢!
补充一点:这部分代码我是放在CM4里的,这可以吗?
Show LessHello,
I am trying to flash littlefs filesystem on the qspi external serial flash memory in XMC7100 V1.1. As I see library mtb-littlefs is not included in the XMC7100 kit but i have included the mtb-littlefs from PSoc6 Kit to my project and in makefile included target as XMC7100 (my board).
BOARD: XMC7100 EVK Lite v1.1
Memory: External QSPI flash memory
These are the errors when I try to builld the file:
Initializing build: mtb-example-psoc6-filesystem-littlefs-freertos Debug APP_KIT_XMC71_EVK_LITE_V1 GCC_ARM
Prebuild operations complete
Auto-discovery in progress...
Auto-discovery complete
Commencing build operations...
Tools Directory: C:/Users/Prasad/ModusToolbox/tools_3.2
"Using linker bsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/COMPONENT_/TOOLCHAIN_GCC_ARM/linker.ld"
Constructing build rules...
Build rules construction complete
==============================================================================
= Building application =
==============================================================================
Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 223 file(s)
Compiling ../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c -DCOMPONENT_APP_KIT_XMC71_EVK_LITE_V1 -DCOMPONENT_CAT1 -DCOMPONENT_CAT1C -DCOMPONENT_CAT1C4M -DCOMPONENT_CM7 -DCOMPONENT_CM7_0 -DCOMPONENT_Debug -DCOMPONENT_FREERTOS -DCOMPONENT_GCC_ARM -DCOMPONENT_MW_ABSTRACTION_RTOS -DCOMPONENT_MW_CAT1CM0P -DCOMPONENT_MW_CLIB_SUPPORT -DCOMPONENT_MW_CMSIS -DCOMPONENT_MW_CORE_LIB -DCOMPONENT_MW_CORE_MAKE -DCOMPONENT_MW_FREERTOS -DCOMPONENT_MW_MTB_HAL_CAT1 -DCOMPONENT_MW_MTB_LITTLEFS -DCOMPONENT_MW_MTB_PDL_CAT1 -DCOMPONENT_MW_RECIPE_MAKE_CAT1C -DCOMPONENT_MW_RETARGET_IO -DCOMPONENT_RTOS_AWARE -DCOMPONENT_SOFTFP -DCOMPONENT_XMC7x_CM0P_SLEEP -DCORE_NAME_CM7_0=1 -DCY_APPNAME_mtb_example_psoc6_filesystem_littlefs_freertos -DCY_RETARGET_IO_CONVERT_LF_TO_CRLF -DCY_SUPPORTS_DEVICE_VALIDATION -DCY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V1 -DCY_USING_HAL -DDEBUG -DLFS_THREADSAFE -DTARGET_APP_KIT_XMC71_EVK_LITE_V1 -DXMC7100D_F176K4160 -I. -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1 -Ibsps -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config/GeneratedSource -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config -Ilibs/abstraction-rtos/include -Ilibs/abstraction-rtos -Ilibs/abstraction-rtos/include/COMPONENT_FREERTOS -Ilibs/cat1cm0p/COMPONENT_CAT1C -Ilibs/cat1cm0p -Ilibs/clib-support -Ilibs/clib-support/TOOLCHAIN_GCC_ARM -Ilibs/cmsis/Core/Include -Ilibs/cmsis/Core -Ilibs/cmsis -Ilibs/core-lib/include -Ilibs/core-lib -Ilibs/freertos/Source/include -Ilibs/freertos/Source -Ilibs/freertos -Ilibs/freertos/Source/portable/COMPONENT_CM7 -Ilibs/freertos/Source/portable -Ilibs/freertos/Source/portable/COMPONENT_CM7/TOOLCHAIN_GCC_ARM -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/pin_packages -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C -Ilibs/mtb-hal-cat1 -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers -Ilibs/mtb-hal-cat1/include -Ilibs/mtb-hal-cat1/include_pvt -Ilibs/mtb-hal-cat1/source -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C -Ilibs/mtb-pdl-cat1/devices -Ilibs/mtb-pdl-cat1 -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip -Ilibs/mtb-pdl-cat1/drivers/include -Ilibs/mtb-pdl-cat1/drivers -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet/include -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet -Ilibs/mtb-pdl-cat1/drivers/third_party -Ilibs/retarget-io -I../mtb_shared/mtb-littlefs/latest-v2.X/bd -I../mtb_shared/mtb-littlefs/latest-v2.X -I../mtb_shared/mtb-littlefs/latest-v2.X/include
../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c:487:5: error: 'cy_stc_smif_mem_device_cfg_t' has no member named 'mergeTimeout'
487 | .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
| ^
make[1]: *** [libs/core-make/make/core/build.mk:283: C:/Users/Prasad/mtw/Littlefs_Filesystem/Littlefs_Filesystem/build/APP_KIT_XMC71_EVK_LITE_V1/Debug/ext/mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.o] Error 1
make: *** [libs/core-make/make/core/main.mk:385: secondstage_build] Error 2
"C:/Users/Prasad/ModusToolbox/tools_3.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/Prasad/ModusToolbox/tools_3.2 CY_IDE_BT_TOOLS_DIR= -j8 --output-sync all" terminated with exit code 2. Build might be incomplete.
When I comment the line:
#if (CY_IP_MXSMIF_VERSION >= 2)
/** Continuous transfer merge timeout.
* After this period the memory device is deselected. A later transfer, even from a
* continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
* This configuration parameter is available for CAT1B devices. */
//.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
#endif /* CY_IP_MXSMIF_VERSION */
I get failed to creat spi device block:
Could someone help me with ".mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE" error?
When using the mtb-littlefs through the mtb-shared, how do I enable the cy_hal, freertos and thread in make file?
I tried to add the necessary comments on my application makefile but it is not enabling the corresponding if condition in the files in mtb-shared folder/mtb-littlefs!
best regard,
PrasadA
Show Less
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TraveoII
UART buadrate Setting
by chandan1995 Jun 19, 2023