Nor Flash Forum Discussions

I have plan to use the S29GL512S NOR Parallel Flash with Cyclone V E FPGA. Can you please provide the information that this memory be functionality supported with Intel Cyclone V E FPGAs?

Migrating from MX25L25645G to S25FL064L.
Used with renesas RA6M5 no access to S25FL064L but MX25L25645G is OK.
The command set looks to be equal.
Any hints to make it work ?
BR
PrebenG

Hello, we bought S29AL016J70BFI010 from Mouser,  week code on label is 2306+, but chip marking show 2308+, who can help to advice why weekcode are different?

Has anyone been able to obtain the new SEMPER™ Nano S25FS256T Memory Module (EVAL-S25FS256T)?  I can't find these at any distributors yet.

I was using S29PL064J55BFI120, but it became EOL. As an alternative, we are considering whether S29PL064J55BFI070 can be used.

I read the datasheets, but I could not understand if there is a difference between the two devices. What is the difference between these?

Thanks,
Tetsuo

Hello team,

Please see below question from the customer:

We are currently using S25FS512S and S25HL512T on our designs.

Our application requires the need to change the addressing mode from 3-bytes to 4-bytes and then back to 3-bytes. The difficulty we are having right now is changing the addressing mode from 4-bytes back to 3-bytes. 

Our understanding is that to exit 4-byte mode, we need either a HW or SW reset. Fortunately we don't have the HW reset connected to the processor, we need to go with the SW reset route. We are running our device in QSPI mode.

Is my understanding correct that we need to send the following commands?

Mode Bit Reset (MBR FFh)

Software Reset Enable (RSTEN 66h) 

Software Reset (RST 99h)   

Is there anything else we should be aware of?

Hi,

Please allow me to confirm the address latch timing for the S29GL.

[A] S29GL064N90TFI020
[B] S29GL064S70TFI020

[Q1]
Section 8.2 of [A]'s datasheet states "All addresses are latched on the falling edge of CE#".
Is there any timing for address latch other than CE# falling?
I would like to confirm the address latch timing when CE# falls before the address is determined.

[Q2]
The [B]'s datasheet no longer mentions "All addresses are latched on the falling edge of CE#".
Is the timing at which the address is latched different for [B] than for [A]?
Please tell us when the address is latched.

Best Regards,
Kumada