Nor Flash Forum Discussions

Dear community:

For an ongoing production, I'm trying to source the S25FL512SAGMFI010 NOR FLASH but it's very hard to find stock.

I can't figure in the datasheet if the DDR version of the same product can be used in single data rate applications (standard 4 wire SPI). The part number in which I'm interested is the following: S25FL512SDPMFIG11.

Thanks in advance!!

Diego.

MX25L6405D SPI Flash memory used in device running the eCos operating system. I'm trying to read a required area of SPI flash memory, so I need to find the System Memory Addresses of SPI Flash memory,  I want to find where the flash is mapped into System memory (system address space) and read the chunks.

For example, show flash command returns the following info:

Flash Device Information:

  CFI Compliant: no
  Command Set: Generic SPI Flash
  Device/Bus Width: x16
Little Word Endian: no
  Fast Bulk Erase: no
  Multibyte Write: 256 bytes max
  Phys base address: 0xbadf1a5
Uncached Virt addr: 0x1badf1a5
  Cached Virt addr: 0x2badf1a5
  Number of blocks: 129
  Total size: 8388608 bytes, 8 Mbytes
  Current mode: Read Array
  Device Size: 8388608, Write buffer: 256, Busy bit:

  Size Device Device Region
Block kB Address Offset Offset Region Allocation
----- ---- ---------- ----------- --------- -----------------
  0 32 0x1badf1a5 0 0 Bootloader (32768 bytes)
  1 32 0x1bae71a5 32768 ??? {unassigned}
  2 64 0x1baef1a5 65536 0 Permanent NonVol (65536 bytes)
  3 64 0x1baff1a5 131072 0 Image1
  4 64 0x1bb0f1a5 196608 65536 Image1
  5 64 0x1bb1f1a5 262144 131072 Image1
  6 64 0x1bb2f1a5 327680 196608 Image1
  7 64 0x1bb3f1a5 393216 262144 Image1
  .. .. ........
  127 64 0x1c2bf1a5 8257536 4063232 Image2 (4128768 bytes)
  128 64 0x1c2cf1a5 8323072 0 Dynamic NonVol (65536 bytes)

But 'Device Address' in above table is not a System memory address, but seems, the address of the hardware device used to access the SPI chip by the OS and bootloader.

So when I tried to read memory, any address, for example: readmem -s 4 -n 16384 0x1baef1a5

it always returns errors: ERROR - Address.

Please advice how to find the System memory addresses, where the SPI flash is mapped into System memory.

We are Shipping S29GL256P10FFI020 on regular basis and customer is looking for reflow profile for S29GL256P10FFI020.

Please help to get the reflow profile.

When using S25FL512S (NOR flash) with Xilinx Virtex 7 is it recommended to use same VIO supply as SPI bank supply on Virtex 7?

According to Connecting Cypress SPI Serial Flash to Configure Xilinx FPGAs document:

"Because tPU is an order of magnitude less than TPOR, the SPI flash becomes ready before the FPGA issues the read command if the same power rail supplies both FPGA and SPI flash. If not, a countermeasure may be needed".

What will happen if the voltage to flash becomes active after the SPI bank voltage on FPGA?

Hi All,

We are using S25FL512SAGMFIR11 in our design.

where we can get the Thermal resistance for junction to case and junction to base??

Thanks,

Ramesh M

The Cypress parallel NOR Flashes have a lot of advanced programming features such as the OTP Password register that are not covered by generic mtd cfi_flash.c code.

Does Cypress have source code available that demonstrates the command set of the S29GL01GS/ S29GL512S, particularly with regards to programming the devices?

i am using S29GL512M nor flash, it was working ok initially but now im not able to erase it ,it is showing error in erasing.

Hi,

I am looking for the Linux patch to support the S70GL02GS Flash.  According to this KB article (S70GL02GS Support Under Linux - KBA218976 ), you have to create a Support Case to receive the patch.  I have done so, but I have only received automated replies so far.

I am also interested in how to specify the S70GL02GS in the Device Tree Source (.dts) file that Linux parses when it is loaded.  For a typical CFI-compatible 2Mbit, 128Mx16 NOR Flash, I would expect its entry to look something like this:

  norflash@0,0 {

   #address-cells = <0x1>;

   #size-cells = <0x1>;

   compatible = "cfi-flash";

   reg = <0x0 0x0 0x10000000>;

   bank-width = <0x2>;

   device-width = <0x1>;

But the S70GL02GS is actually two 1Mbit NOR Flash die (S29GL01GS) in the same package.  So there is one external chip select, but internally there are two address-mapped regions that have independent protected sectors and control/status registers.  Perhaps there would be two "reg" declarations to account for the two sets of control registers, one at byte offset 0x8000000?

In data sheet "10.4.3 Power-Up and Power-Down"

It is written "At no time should VIO be greater then 200 mV above VCC (VCC >= VIO - 200 mV)."

Not even 10 msec?