S29AL016J70TFI02: Boot flash erase timing varying chip to chip.

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ViRa_4650396
Level 1
Level 1

Hi,

We are using the below mentioned Boot Flash chip for our application.

     Part no                     -S29AL016J70TFI02 (TSOP-48)

     Top Marking:

                    1st line      - S29AL016J70TFI02

                    2nd line     - 838BB134 M

                    3rd line     - ©07 SPANSION

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Issue: The boot flash chip S29AL016J70TFI02 is mounted in two boards. Both the boards are tested for chip erase in room temperature. We observed that the chip erase timing for both the IC's are different. We probed at RY/BY# assertion and found below two different chip erase timings.

Chip 1: 15.5s

Chip 2: 19.1s

What would be the reason for the exceeding the typical chip erase time as mentioned in the datasheet "18. Erase and Programming Performance".

With regards,

Vigneshwar Raj

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1 Solution

Hello,

I discussed this issue with our product experts. The chip erase times that you observe from chip 1 (15.5s) and chip 2 (19.5s) are expected values. Our datasheet mention only typical chip erase time (16s), it is the average chip erase time. So, there can be devices with chip erase time more than this typical value. We recommend you to use data# polling and RY/BY# pin to know the completion status of program/erase operations in our device.

Thanks and Regards,

Sudheesh

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3 Replies
SudheeshK
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hello,

Chip erase time can take longer than the maximum chip erase time mentioned in the datasheet when the flash cells are wearing out and the device is end of life. Program and erase operations can take longer than maximum, when the maximum number of program/erase cycles are performed on the device. For the part S29AL016J maximum number of program/erase (endurance) cycles is 1,000,000.

1. Are you testing and observing this issue on a new S29AL016J device? Or, did this issue start to happen after working fine for a time period? Please provide more details.

2. How many devices are showing this issue?

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

The maximum number of program/erase cycles are performed on the

device would be between 15 to 20.

Reply for the questions,

1) This issue is addressed in a new device

2) Upto now we observed in 1 device.

Is there any other parameter we need to check during erase period?

Regards,

Vigneshwar Raj D

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Hello,

I discussed this issue with our product experts. The chip erase times that you observe from chip 1 (15.5s) and chip 2 (19.5s) are expected values. Our datasheet mention only typical chip erase time (16s), it is the average chip erase time. So, there can be devices with chip erase time more than this typical value. We recommend you to use data# polling and RY/BY# pin to know the completion status of program/erase operations in our device.

Thanks and Regards,

Sudheesh

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