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Legacy Microcontrollers

Anonymous
Not applicable

Hello All,

In the Core Test of the STL, the interrupt sub-test for confirms that the function of each stage works correctly in the attached block diagram. This message can learn form former Case #00396744.(Also can refer to the figure).

Recently, TÜV Rheinland have a question. Please we consider the bit error whether or not will cause the unexpected interrupt ?

So I want know if the result of the Core Test is good, that can prove that don't occur bit error or unexpected interrupt ?

Best regards.

Guanghua Zhu.

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1 Solution
Roy_Liu
Moderator
Moderator

STL relevant queries are not suitable to discuss in this community, recommendation is contacting your Cypress sale/support team directly.

Roy Liu

View solution in original post

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2 Replies
Roy_Liu
Moderator
Moderator

STL relevant queries are not suitable to discuss in this community, recommendation is contacting your Cypress sale/support team directly.

Roy Liu

View solution in original post

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Anonymous
Not applicable

OK, I have directly contacted Amy via email. Thanks your reply

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