The QDRII+/DDRII+ SRAMs with ODT have terminations on Data Inputs, BWSb and K/Kb pins. In memory controllers where BWSb signals are always asserted and therefore need to be tied low, each pin needs to be connected via the appropriate termination resistor to ground. In the diagram below we depict the case of a 50 Ω termination. In the event one would like to connect multiple BWSb pins to each other in parallel, the numbers of 50 Ω resistors to ground also need to increase proportionally. In other words, the 50 Ω resistors should be connected in parallel. Alternatively one can reduce the number of 50 Ω resistors by just using a single resistor of the value 50÷N, where N is the number of pins connected in parallel.