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TRAVEO™ T2G Automotive Body Controller - FAQ – GPIO - KBA232509

TRAVEO™ T2G Automotive Body Controller - FAQ – GPIO - KBA232509

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Home Page: TRAVEO™ T2G Automotive Body Controller - FAQ – CDC



2.1  What is the status of unused GPIO pins?

The default mode is High-Z, input buffer is disabled, and no internal pull-up/down resister connected.

2.2  Which GPIO port is available for Slew Rate Control?

Only an enhanced I/O port “GPIO_ENH” supports Slew Rate Control. For standard ports, slew rate can be controlled using drive strength.

See the following for more details:

  • TRAVEO™ T2G Automotive Body Controller Entry Family Architecture Technical Reference Manual (TRM), Document No. 002-19314 Rev. *E. Section 22.6.2, “Slew Rate Control”
  • TRAVEO™ T2G Automotive Body Controller High Family Architecture Technical Reference Manual (TRM), Document No. 002-24401 Rev. *C. Section 22.6.2, “Slew Rate Control”
2.3  Is the GPIO pin connected to the Stepper Motor directly?

Yes. GPIO_SMC is supported specifically for Stepper Motor Control. TCPWM counters supporting SMC are intended to be connected to GPIO_SMC cells in the Input/Output Subsystem, which support a 30-mA drive strength for directly driving stepper motors.

2.4  If CAN and LIN are connected, which are used: GPIO_STD or GPIO_ENH?

There is no restriction to use GPIO_STD or GPIO_ENH for CAN and LIN. The pins for CAN and LIN are mapped to GPIO_STD or GPIO_ENH on the TRAVEO™ T2G device.

  • GPIO Standard. Supports standard automotive signaling with 2.7-V to 5.5-V VDDIO range. GPIO-Standard I/Os have multiple configurable drive levels, drive modes, and selectable input levels.
  • GPIO Enhanced. Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher currents at lower voltages (full I2C timing support and slew rate control).
2.5  What value can be used as output impedance of the GPIO for impedance matching?

You can use IBIS model provided for the device to determine output impedance value. You will need the impedance data of device on the other end. You need to have external series resistance on the signal line based on the output impedance to match the 50 ohms transmission line and avoid reflections. But, the reflection will happen only at the rising and falling edges of the signal and does not depend on the frequency itself, so impedance need not be considered at different frequencies. You can use the IBIS model of the device pin to view the pullup and pulldown VI curves and check if the output impedance is lower than 50 ohms. Then, you can input the IBIS file to the IBIS simulator and do a series resistance sweep simulation and determine the series resistance that gives the best signal integrity.

2.6  If one pin of the device has been used as the input of Smart I/O, can the same pin be used for the output of other peripheral blocks?

No. If the pin is routed for the input of Smart I/O block, the pin's HSIOM registers will be occupied by Smart I/O routing. In this case, the pin cannot be used for output of other peripheral blocks.

2.7 If the pad of one pin is not available on a certain package, can its alternate function be routed to Smart I/O?

If the pad of one pin is not available on a certain package, but its HSIOM and Smart I/O registers are available (see the HSIOM and Smart I/O registers in the respective Registers TRM), you can route its alternate function as input of Smart I/O. Though the unavailable pin can be routed for Smart I/O output too, as the pin’s pad is not available on the package, the output cannot be seen.

2.8  Why cannot SMIF HSIO_ENH pins be configured as GPIO?

All IOSS logic between SMIF and IOs are removed for Address/Data, RWDC, clock of SMIF pins.

The pins with function SPIHB[0,1]_CLK/CLK_M, SPIHB[0,1]_DATA[0-7], SPIHB[0,1]_RWDS have the following limitations:

  • No boundary scan for these IOs.
  • MMIO register cannot control data out, data output enable of the above listed pins.
  • The pins are dedicatedly used for SMIF.
  • No interrupt functionality on above listed pins.