Question: - How does soft reset work in the PCI-DP? - How do you trigger a soft reset? - What is the difference between a regular and soft reset? - What happens to the Operations Registers during soft reset?
Answer: A soft reset allows certain registers to remain unchanged while resetting others. This is different than a regular (hard) reset. One of the advantages of a soft reset is that it keeps the LBUSCFG register at its previously loaded value, meaning the local processor is still configured properly to work with the PCI-DP after a soft reset.
To issue a soft reset, you must write a '1' to bit 1 of Host Control Register (HCTL: Address 0x04E0). When Soft Reset = '1', it will reset all of the Operations Registers according to their reset default values with the following exceptions: - DMACTL (at offset 0x04BC): All bits are reset to '0', except bits PI and W remain unchanged - HINT (at offset 0x04E4): All bits remain unchanged - LINT (at offset 0x04F4): Bit 3 (Host to Local Mailbox) is cleared to 0, all other bits remain unchanged - LBUSCFG (at offset 0x04FC): All bits remain unchanged In addition, as a result of a soft reset: - DQ[31:00] is held at high impedance; - Local bus state machine is held in idle; - DMA state machine is held in idle; - PCI bus state machine mastering access is held in idle; and - FIFO are emptied and flags return to default (empty). If you notice interrupts, do not clear with a soft reset. Instead, you will need to issue a hard reset via the local bus.
