Question: I'm developing FX2 firmware that uses an EP2 1024 byte Interrupt mode endpoint. I'm trying to send 1024 byte packets out the GPIF at the highest possible speed after determining that the target FIFOs are not full. The GPIF waveform has write enables and mode bits in the CTL signals, so I can't go through IDLE except at packet boundaries without disrupting the target. I've tried AUTOOUT=1, and it seems the FX2 is sending multiple 1024 byte packets without going through IDLE. I need to go through IDLE every 1024 bytes to test the target FIFO. How?
In this case, you should:
1) Have the 8051 examine the GPIFREADYSTAT register to determine if the target FIFOs are not full. 2) Once this condition has been established, set up the GPIFTC[B1:B0] registers for 1024. 3) Check that the GPIF is idle, then launch the FIFO Read waveform, each time passing through IDLE. 4) Repeat the process for multiple 1024 block transfers.