Read and Write with Single Internal Counter for Synchronous Dual port SRAM's
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Jun 11, 2011
12:38 PM
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Jun 11, 2011
12:38 PM
Question: What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?
Answer:
The internal counter will indeed increment no matter what type of operation you are carrying out. The internal counters are blind to what is occurring outside the ADS#, CNTEN#, CNT/MSK#, and CNTRST# (and clock) signals. So in the situation described above, the result would be:
Clock Cycle | Operation | Result |
1 | Write | Write to address n |
2 | Read | Read from address n+1 |
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