Read / Write control signals on unidirectional FIFOs
Question: Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
Although the data path is unidirectional from port A to port B, the mailboxes are bidirectional. Mail1 register handles a 36-bit data going from port A to port B while Mail2 register handles a 36-bit data from port B to port A. Therefore, a R/W# signal is required for each port.