Question: Is there a way to keep the CLK output running when the RESET input is asserted? If not, what is the maximum time from the de-assertion of RESET until the CLK output is stable again?
When asserted the "Reset" pin is hardware reset for the chip. There is no way to keep the "CLK output" running during the power-up sequence of the device. The internal PLL stabilizes approximately 200 us after VCC has reached 3.3V (CY7C68000 Datasheet, Page 5 of 17, section 3.4). When using a crystal, the minimum reset time (tRESET) is 1.9 ms. (CY7C68000 Datasheet, page 12 of 17, Table 8-1). TX2 is currently obsolete, the functional replacement is TX2UL. All the related collaterals of TX2UL can be found in the link here.