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Parity during read and write

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Parity during read and write

Question: How is parity generated during reads and write?



 In all of cypress's srams, parity check logic is not implemented on the part. The parity check is upto the discretion of the customer. If they decide not to use the parity feature then, they can use the extra 4 I/O bits as data bits. For eg; the CY7C1347B is a 128K x 36 SRAM. So, generally what most of our customers do is, if they decide to include parity check feature, they will use the four bytes(8 bits each) for data and the extra 4 I/O lines for parity check. Even parity or Odd parity check has to be decided and a logic to generate the parity bit in the memory controller has to be implemented. When a write is intiated, the external memory controller will decide (depending on the data of the 8 bits and whether to check for even or odd parity) to write either a '1' or a '0' on the parity bit. When a read is intiated, the parity decoder logic in the external memory controller will read the 8 bits coming and see whether the parity bit should be a 1 or a zero and flag if there is any discrepancy found.

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‎Mar 01, 2011 10:39 AM
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