Parameters determining the minimum and maximum sample rate of PSoC 3/5 Del Sig ADC
Question: What determines the minimum and maximum sample rate of PSoC 3/5 Del Sig ADC?
The maximum and minimum ADC sample rate (Conversion Rate) you can set depends on the maximum Clock the ADC can take, ADC Resolution, Conversion mode and the buffer gain.
The ADC input clock (Clock Frequency Parameter) cannot go lower than 128kHz and greater than 3.072 MHz(for >= 16-bits) / 4.8MHz (for >=12 bits < 16- bits) / 6.144 MHz (for <12 bits).
The user module datasheet shows the maximum and minimum sample rate that can be achieved with a specified Resolution and Conversion mode, based on the above clock requirements. The table is valid only for a unity buffer gain. For buffer gains greater than 1, the maximum sample rate that can be achieved specified in the table should be divided by the buffer gain.
For eg, 16-bit ADC in continuous mode for a unity buffer gain can have a maximum sample rate of 48 ksps.
16-bit ADC in continuous mode for a buffer gain of 8 can have a maximum sample rate of 6 ksps only.