Question: What is the behavior of the CY22393 clock outputs (CLKA-CLKE) when the reference input clock at pin XTALIN fails and is in a static state?
Answer: If the XTALIN input stops oscillating and is driven high or low, the CLK outputs will be driven high or low. The output level (high or low) is random and is not related to the input level, nor to the levels of the other outputs. If the XTALIN pin is floating, the output behavior is less predictable. Typically the outputs will continue to oscillate, usually at a increased but unstable frequency. However, it is also possible for the outputs to stop oscillating, or to alternately start and stop oscillating.
The following devices have the same behavior: CY22381, CY22392, CY22393, CY22394, CY22395.
